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https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-21 03:54:34 +00:00
hikey: drop LOAD_IMAGE v1
Since LOAD_IMAGE_V2 is always enabled in HiKey platform. Drop LOAD_IMAGE v1 to simplify code. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
This commit is contained in:
parent
cde9f4f41f
commit
103c213c0d
5 changed files with 8 additions and 226 deletions
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@ -58,7 +58,6 @@ meminfo_t *bl1_plat_sec_mem_layout(void)
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return &bl1_tzram_layout;
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return &bl1_tzram_layout;
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}
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}
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#if LOAD_IMAGE_V2
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/*******************************************************************************
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/*******************************************************************************
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* Function that takes a memory layout into which BL2 has been loaded and
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* Function that takes a memory layout into which BL2 has been loaded and
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* populates a new memory layout for BL2 that ensures that BL1's data sections
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* populates a new memory layout for BL2 that ensures that BL1's data sections
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@ -80,7 +79,6 @@ void bl1_init_bl2_mem_layout(const meminfo_t *bl1_mem_layout,
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flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
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flush_dcache_range((unsigned long)bl2_mem_layout, sizeof(meminfo_t));
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}
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}
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#endif /* LOAD_IMAGE_V2 */
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/*
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/*
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* Perform any BL1 specific platform actions.
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* Perform any BL1 specific platform actions.
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@ -94,16 +92,6 @@ void bl1_early_platform_setup(void)
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_base = BL1_RW_BASE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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bl1_tzram_layout.total_size = BL1_RW_SIZE;
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#if !LOAD_IMAGE_V2
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/* Calculate how much RAM BL1 is using and how much remains free */
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bl1_tzram_layout.free_base = BL1_RW_BASE;
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bl1_tzram_layout.free_size = BL1_RW_SIZE;
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reserve_mem(&bl1_tzram_layout.free_base,
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&bl1_tzram_layout.free_size,
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BL1_RAM_BASE,
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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#endif
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INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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INFO("BL1: 0x%lx - 0x%lx [size = %lu]\n", BL1_RAM_BASE, BL1_RAM_LIMIT,
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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BL1_RAM_LIMIT - BL1_RAM_BASE); /* bl1_size */
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}
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}
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -17,11 +17,9 @@
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#include <hisi_mcu.h>
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#include <hisi_mcu.h>
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#include <hisi_sram_map.h>
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#include <hisi_sram_map.h>
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#include <mmio.h>
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#include <mmio.h>
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#if LOAD_IMAGE_V2
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#ifdef SPD_opteed
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#ifdef SPD_opteed
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#include <optee_utils.h>
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#include <optee_utils.h>
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#endif
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#endif
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#endif
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#include <platform_def.h>
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#include <platform_def.h>
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#include <sp804_delay_timer.h>
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#include <sp804_delay_timer.h>
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#include <string.h>
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#include <string.h>
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@ -50,48 +48,11 @@
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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#if !LOAD_IMAGE_V2
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/*******************************************************************************
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* This structure represents the superset of information that is passed to
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* BL31, e.g. while passing control to it from BL2, bl31_params
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* and other platform specific params
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******************************************************************************/
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typedef struct bl2_to_bl31_params_mem {
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bl31_params_t bl31_params;
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image_info_t bl31_image_info;
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image_info_t bl32_image_info;
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image_info_t bl33_image_info;
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entry_point_info_t bl33_ep_info;
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entry_point_info_t bl32_ep_info;
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entry_point_info_t bl31_ep_info;
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} bl2_to_bl31_params_mem_t;
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static bl2_to_bl31_params_mem_t bl31_params_mem;
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meminfo_t *bl2_plat_sec_mem_layout(void)
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{
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return &bl2_tzram_layout;
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}
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void bl2_plat_get_scp_bl2_meminfo(meminfo_t *scp_bl2_meminfo)
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{
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scp_bl2_meminfo->total_base = SCP_BL2_BASE;
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scp_bl2_meminfo->total_size = SCP_BL2_SIZE;
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scp_bl2_meminfo->free_base = SCP_BL2_BASE;
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scp_bl2_meminfo->free_size = SCP_BL2_SIZE;
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}
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#endif /* LOAD_IMAGE_V2 */
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/*******************************************************************************
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/*******************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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* Return 0 on success, -1 otherwise.
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* Return 0 on success, -1 otherwise.
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******************************************************************************/
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******************************************************************************/
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#if LOAD_IMAGE_V2
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int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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int plat_hikey_bl2_handle_scp_bl2(image_info_t *scp_bl2_image_info)
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#else
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int bl2_plat_handle_scp_bl2(struct image_info *scp_bl2_image_info)
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#endif
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{
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{
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/* Enable MCU SRAM */
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/* Enable MCU SRAM */
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hisi_mcu_enable_sram();
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hisi_mcu_enable_sram();
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@ -161,7 +122,6 @@ uint32_t hikey_get_spsr_for_bl33_entry(void)
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}
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}
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#endif /* AARCH32 */
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#endif /* AARCH32 */
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#if LOAD_IMAGE_V2
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int hikey_bl2_handle_post_image_load(unsigned int image_id)
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int hikey_bl2_handle_post_image_load(unsigned int image_id)
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{
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{
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int err = 0;
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int err = 0;
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@ -222,144 +182,6 @@ int bl2_plat_handle_post_image_load(unsigned int image_id)
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return hikey_bl2_handle_post_image_load(image_id);
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return hikey_bl2_handle_post_image_load(image_id);
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}
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}
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#else /* LOAD_IMAGE_V2 */
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bl31_params_t *bl2_plat_get_bl31_params(void)
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{
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bl31_params_t *bl2_to_bl31_params = NULL;
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/*
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* Initialise the memory for all the arguments that needs to
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* be passed to BL3-1
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*/
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memset(&bl31_params_mem, 0, sizeof(bl2_to_bl31_params_mem_t));
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/* Assign memory for TF related information */
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bl2_to_bl31_params = &bl31_params_mem.bl31_params;
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SET_PARAM_HEAD(bl2_to_bl31_params, PARAM_BL31, VERSION_1, 0);
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/* Fill BL3-1 related information */
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bl2_to_bl31_params->bl31_image_info = &bl31_params_mem.bl31_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl31_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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/* Fill BL3-2 related information if it exists */
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#ifdef BL32_BASE
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bl2_to_bl31_params->bl32_ep_info = &bl31_params_mem.bl32_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_ep_info, PARAM_EP,
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VERSION_1, 0);
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bl2_to_bl31_params->bl32_image_info = &bl31_params_mem.bl32_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl32_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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#endif
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/* Fill BL3-3 related information */
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bl2_to_bl31_params->bl33_ep_info = &bl31_params_mem.bl33_ep_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_ep_info,
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PARAM_EP, VERSION_1, 0);
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/* BL3-3 expects to receive the primary CPU MPID (through x0) */
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bl2_to_bl31_params->bl33_ep_info->args.arg0 = 0xffff & read_mpidr();
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bl2_to_bl31_params->bl33_image_info = &bl31_params_mem.bl33_image_info;
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SET_PARAM_HEAD(bl2_to_bl31_params->bl33_image_info, PARAM_IMAGE_BINARY,
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VERSION_1, 0);
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return bl2_to_bl31_params;
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}
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struct entry_point_info *bl2_plat_get_bl31_ep_info(void)
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{
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#if DEBUG
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bl31_params_mem.bl31_ep_info.args.arg1 = HIKEY_BL31_PLAT_PARAM_VAL;
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#endif
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return &bl31_params_mem.bl31_ep_info;
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}
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void bl2_plat_set_bl31_ep_info(image_info_t *image,
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entry_point_info_t *bl31_ep_info)
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{
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SET_SECURITY_STATE(bl31_ep_info->h.attr, SECURE);
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bl31_ep_info->spsr = SPSR_64(MODE_EL3, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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}
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/*******************************************************************************
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* Before calling this function BL32 is loaded in memory and its entrypoint
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* is set by load_image. This is a placeholder for the platform to change
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* the entrypoint of BL32 and set SPSR and security state.
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* On Hikey we only set the security state of the entrypoint
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******************************************************************************/
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#ifdef BL32_BASE
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void bl2_plat_set_bl32_ep_info(image_info_t *bl32_image_info,
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entry_point_info_t *bl32_ep_info)
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{
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SET_SECURITY_STATE(bl32_ep_info->h.attr, SECURE);
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/*
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* The Secure Payload Dispatcher service is responsible for
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* setting the SPSR prior to entry into the BL32 image.
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*/
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bl32_ep_info->spsr = 0;
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}
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/*******************************************************************************
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* Populate the extents of memory available for loading BL32
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******************************************************************************/
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void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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{
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/*
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* Populate the extents of memory available for loading BL32.
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*/
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bl32_meminfo->total_base = BL32_BASE;
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bl32_meminfo->free_base = BL32_BASE;
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bl32_meminfo->total_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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bl32_meminfo->free_size =
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(TSP_SEC_MEM_BASE + TSP_SEC_MEM_SIZE) - BL32_BASE;
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}
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#endif /* BL32_BASE */
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void bl2_plat_set_bl33_ep_info(image_info_t *image,
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entry_point_info_t *bl33_ep_info)
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{
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unsigned long el_status;
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unsigned int mode;
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/* Figure out what mode we enter the non-secure world in */
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el_status = read_id_aa64pfr0_el1() >> ID_AA64PFR0_EL2_SHIFT;
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el_status &= ID_AA64PFR0_ELX_MASK;
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if (el_status)
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mode = MODE_EL2;
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else
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mode = MODE_EL1;
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/*
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* TODO: Consider the possibility of specifying the SPSR in
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* the FIP ToC and allowing the platform to have a say as
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* well.
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*/
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bl33_ep_info->spsr = SPSR_64(mode, MODE_SP_ELX,
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DISABLE_ALL_EXCEPTIONS);
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SET_SECURITY_STATE(bl33_ep_info->h.attr, NON_SECURE);
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}
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void bl2_plat_flush_bl31_params(void)
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{
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flush_dcache_range((unsigned long)&bl31_params_mem,
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sizeof(bl2_to_bl31_params_mem_t));
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}
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DDR_BASE;
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bl33_meminfo->total_size = DDR_SIZE;
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bl33_meminfo->free_base = DDR_BASE;
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bl33_meminfo->free_size = DDR_SIZE;
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}
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#endif /* LOAD_IMAGE_V2 */
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static void reset_dwmmc_clk(void)
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static void reset_dwmmc_clk(void)
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{
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{
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unsigned int data;
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unsigned int data;
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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return NULL;
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return NULL;
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}
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}
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#if LOAD_IMAGE_V2
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void bl31_early_platform_setup(void *from_bl2,
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void bl31_early_platform_setup(void *from_bl2,
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void *plat_params_from_bl2)
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void *plat_params_from_bl2)
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#else
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void bl31_early_platform_setup(bl31_params_t *from_bl2,
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void *plat_params_from_bl2)
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#endif
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{
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{
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/* Initialize the console to provide early debug support */
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/* Initialize the console to provide early debug support */
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console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
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cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_init(CCI400_BASE, cci_map, ARRAY_SIZE(cci_map));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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cci_enable_snoop_dvm_reqs(MPIDR_AFFLVL1_VAL(read_mpidr_el1()));
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#if LOAD_IMAGE_V2
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/*
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/*
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* Check params passed from BL2 should not be NULL,
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* Check params passed from BL2 should not be NULL,
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*/
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*/
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if (bl33_ep_info.pc == 0)
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if (bl33_ep_info.pc == 0)
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panic();
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panic();
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#else /* LOAD_IMAGE_V2 */
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/*
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* Check params passed from BL2 should not be NULL,
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*/
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* Copy BL3-2 and BL3-3 entry point information.
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* They are stored in Secure RAM, in BL2's address space.
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*/
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bl32_ep_info = *from_bl2->bl32_ep_info;
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bl33_ep_info = *from_bl2->bl33_ep_info;
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#endif /* LOAD_IMAGE_V2 */
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}
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}
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void bl31_plat_arch_setup(void)
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void bl31_plat_arch_setup(void)
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/*
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||||
*
|
*
|
||||||
* SPDX-License-Identifier: BSD-3-Clause
|
* SPDX-License-Identifier: BSD-3-Clause
|
||||||
*/
|
*/
|
||||||
|
@ -113,13 +113,11 @@
|
||||||
#define BL32_DRAM_BASE DDR_SEC_BASE
|
#define BL32_DRAM_BASE DDR_SEC_BASE
|
||||||
#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
|
#define BL32_DRAM_LIMIT (DDR_SEC_BASE+DDR_SEC_SIZE)
|
||||||
|
|
||||||
#if LOAD_IMAGE_V2
|
|
||||||
#ifdef SPD_opteed
|
#ifdef SPD_opteed
|
||||||
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
/* Load pageable part of OP-TEE at end of allocated DRAM space for BL32 */
|
||||||
#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
|
#define HIKEY_OPTEE_PAGEABLE_LOAD_BASE (BL32_DRAM_LIMIT - HIKEY_OPTEE_PAGEABLE_LOAD_SIZE) /* 0x3FC0_0000 */
|
||||||
#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
#define HIKEY_OPTEE_PAGEABLE_LOAD_SIZE 0x400000 /* 4MB */
|
||||||
#endif
|
#endif
|
||||||
#endif
|
|
||||||
|
|
||||||
#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
|
#if (HIKEY_TSP_RAM_LOCATION_ID == HIKEY_DRAM_ID)
|
||||||
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
#define TSP_SEC_MEM_BASE BL32_DRAM_BASE
|
||||||
|
|
|
@ -1,5 +1,5 @@
|
||||||
#
|
#
|
||||||
# Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
# Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||||
#
|
#
|
||||||
# SPDX-License-Identifier: BSD-3-Clause
|
# SPDX-License-Identifier: BSD-3-Clause
|
||||||
#
|
#
|
||||||
|
@ -69,7 +69,8 @@ BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
|
||||||
plat/hisilicon/hikey/hikey_bl1_setup.c \
|
plat/hisilicon/hikey/hikey_bl1_setup.c \
|
||||||
plat/hisilicon/hikey/hikey_io_storage.c
|
plat/hisilicon/hikey/hikey_io_storage.c
|
||||||
|
|
||||||
BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
|
BL2_SOURCES += common/desc_image_load.c \
|
||||||
|
drivers/arm/sp804/sp804_delay_timer.c \
|
||||||
drivers/delay_timer/delay_timer.c \
|
drivers/delay_timer/delay_timer.c \
|
||||||
drivers/io/io_block.c \
|
drivers/io/io_block.c \
|
||||||
drivers/io/io_fip.c \
|
drivers/io/io_fip.c \
|
||||||
|
@ -77,22 +78,18 @@ BL2_SOURCES += drivers/arm/sp804/sp804_delay_timer.c \
|
||||||
drivers/emmc/emmc.c \
|
drivers/emmc/emmc.c \
|
||||||
drivers/synopsys/emmc/dw_mmc.c \
|
drivers/synopsys/emmc/dw_mmc.c \
|
||||||
plat/hisilicon/hikey/aarch64/hikey_helpers.S \
|
plat/hisilicon/hikey/aarch64/hikey_helpers.S \
|
||||||
|
plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
|
||||||
plat/hisilicon/hikey/hikey_bl2_setup.c \
|
plat/hisilicon/hikey/hikey_bl2_setup.c \
|
||||||
plat/hisilicon/hikey/hikey_security.c \
|
plat/hisilicon/hikey/hikey_security.c \
|
||||||
plat/hisilicon/hikey/hikey_ddr.c \
|
plat/hisilicon/hikey/hikey_ddr.c \
|
||||||
|
plat/hisilicon/hikey/hikey_image_load.c \
|
||||||
plat/hisilicon/hikey/hikey_io_storage.c \
|
plat/hisilicon/hikey/hikey_io_storage.c \
|
||||||
plat/hisilicon/hikey/hisi_dvfs.c \
|
plat/hisilicon/hikey/hisi_dvfs.c \
|
||||||
plat/hisilicon/hikey/hisi_mcu.c
|
plat/hisilicon/hikey/hisi_mcu.c
|
||||||
|
|
||||||
ifeq (${LOAD_IMAGE_V2},1)
|
|
||||||
BL2_SOURCES += plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
|
|
||||||
plat/hisilicon/hikey/hikey_image_load.c \
|
|
||||||
common/desc_image_load.c
|
|
||||||
|
|
||||||
ifeq (${SPD},opteed)
|
ifeq (${SPD},opteed)
|
||||||
BL2_SOURCES += lib/optee/optee_utils.c
|
BL2_SOURCES += lib/optee/optee_utils.c
|
||||||
endif
|
endif
|
||||||
endif
|
|
||||||
|
|
||||||
HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
HIKEY_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||||
drivers/arm/gic/v2/gicv2_main.c \
|
drivers/arm/gic/v2/gicv2_main.c \
|
||||||
|
|
Loading…
Add table
Reference in a new issue