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https://github.com/ARM-software/arm-trusted-firmware.git
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ble: ap807: Switch to PLL mode and update CPU frequency
- Update CPU frequency on AP807 to 2GHz for SAR 0x0. - Increase AVS to 0.88V for 2GHz clock Change-Id: Ic945b682ab2f8543e34294bfc56c3eae2c5e0c8e Signed-off-by: Christine Gharzuzi <chrisg@marvell.com> Signed-off-by: Konstantin Porotchkin <kostap@marvell.com>
This commit is contained in:
Christine Gharzuzi
Konstantin Porotchkin
parent
55df84f974
commit
1020e0d326
4 changed files with 175 additions and 75 deletions
101
drivers/marvell/ap807_clocks_init.c
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101
drivers/marvell/ap807_clocks_init.c
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@ -0,0 +1,101 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <a8k_plat_def.h>
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#include <aro.h>
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#include <delay_timer.h>
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#include <mmio.h>
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/* Notify bootloader on DRAM setup */
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#define AP807_CPU_ARO_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82A8 + (0xA58 * (cluster)))
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/* 0 - ARO clock is enabled, 1 - ARO clock is disabled */
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#define AP807_CPU_ARO_CLK_EN_OFFSET 0
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#define AP807_CPU_ARO_CLK_EN_MASK (0x1 << AP807_CPU_ARO_CLK_EN_OFFSET)
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/* 0 - ARO is the clock source, 1 - PLL is the clock source */
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#define AP807_CPU_ARO_SEL_PLL_OFFSET 5
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#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
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/* AP807 clusters count */
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#define AP807_CLUSTER_NUM 2
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/* PLL frequency values */
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#define PLL_FREQ_1200 0x2AE5F002 /* 1200 */
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#define PLL_FREQ_2000 0x2FC9F002 /* 2000 */
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#define PLL_FREQ_2200 0x2AC57001 /* 2200 */
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#define PLL_FREQ_2400 0x2AE5F001 /* 2400 */
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/* CPU PLL control registers */
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#define AP807_CPU_PLL_CTRL(cluster) \
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(MVEBU_RFU_BASE + 0x82E0 + (0x8 * (cluster)))
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#define AP807_CPU_PLL_PARAM(cluster) AP807_CPU_PLL_CTRL(cluster)
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#define AP807_CPU_PLL_CFG(cluster) (AP807_CPU_PLL_CTRL(cluster) + 0x4)
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#define AP807_CPU_PLL_CFG_BYPASS_MODE (0x1)
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#define AP807_CPU_PLL_CFG_USE_REG_FILE (0x1 << 9)
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static void pll_set_freq(unsigned int freq_val)
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{
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int i;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE |
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AP807_CPU_PLL_CFG_BYPASS_MODE);
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mmio_write_32(AP807_CPU_PLL_PARAM(i), freq_val);
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mmio_write_32(AP807_CPU_PLL_CFG(i),
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AP807_CPU_PLL_CFG_USE_REG_FILE);
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}
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}
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/* Switch to ARO from PLL in ap807 */
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static void aro_to_pll(void)
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{
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unsigned int reg;
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int i;
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for (i = 0 ; i < AP807_CLUSTER_NUM ; i++) {
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/* switch from ARO to PLL */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= AP807_CPU_ARO_SEL_PLL_MASK;
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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mdelay(100);
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/* disable ARO clk driver */
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reg = mmio_read_32(AP807_CPU_ARO_CTRL(i));
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reg |= (AP807_CPU_ARO_CLK_EN_MASK);
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mmio_write_32(AP807_CPU_ARO_CTRL(i), reg);
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}
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}
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/* switch from ARO to PLL
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* in case of default frequency option, configure PLL registers
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* to be aligned with new default frequency.
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*/
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void ap807_clocks_init(unsigned int freq_option)
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{
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/* Switch from ARO to PLL */
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aro_to_pll();
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/* Modifications in frequency table:
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* 0x0: 764x: change to 2000 MHz.
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* 0x2: 744x change to 1800 MHz, 764x change to 2200/2400.
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* 0x3: 3900/744x/764x change to 1200 MHz.
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*/
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switch (freq_option) {
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case CPU_2000_DDR_1200_RCLK_1200:
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pll_set_freq(PLL_FREQ_2000);
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break;
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default:
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break;
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}
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}
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14
include/drivers/marvell/ap807_clocks_init.h
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14
include/drivers/marvell/ap807_clocks_init.h
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@ -0,0 +1,14 @@
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/*
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* Copyright (C) 2018 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef AP807_INIT_CLOCKS_H
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#define AP807_INIT_CLOCKS_H
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void ap807_clocks_init(unsigned int freq_option);
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#endif /* AP807_INIT_CLOCKS_H */
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@ -60,14 +60,15 @@ BLE_PORTING_SOURCES := $(PLAT_FAMILY_BASE)/$(PLAT)/board/dram_port.c \
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MARVELL_MOCHI_DRV += $(MARVELL_DRV_BASE)/mochi/cp110_setup.c
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BLE_SOURCES := drivers/mentor/i2c/mi2cv.c \
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$(PLAT_COMMON_BASE)/plat_ble_setup.c \
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$(MARVELL_MOCHI_DRV) \
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$(PLAT_COMMON_BASE)/plat_pm.c \
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$(MARVELL_DRV_BASE)/thermal.c \
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$(PLAT_COMMON_BASE)/plat_thermal.c \
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$(BLE_PORTING_SOURCES) \
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$(MARVELL_DRV_BASE)/ccu.c \
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BLE_SOURCES := drivers/mentor/i2c/mi2cv.c \
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$(PLAT_COMMON_BASE)/plat_ble_setup.c \
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$(MARVELL_MOCHI_DRV) \
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$(PLAT_COMMON_BASE)/plat_pm.c \
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$(MARVELL_DRV_BASE)/ap807_clocks_init.c \
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$(MARVELL_DRV_BASE)/thermal.c \
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$(PLAT_COMMON_BASE)/plat_thermal.c \
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$(BLE_PORTING_SOURCES) \
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$(MARVELL_DRV_BASE)/ccu.c \
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$(MARVELL_DRV_BASE)/io_win.c
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BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \
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@ -15,14 +15,15 @@
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#include <mv_ddr_if.h>
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#include <mvebu_def.h>
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#include <plat_marvell.h>
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#include "ap807_clocks_init.h"
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/* Register for skip image use */
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#define SCRATCH_PAD_REG2 0xF06F00A8
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#define SCRATCH_PAD_SKIP_VAL 0x01
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#define NUM_OF_GPIO_PER_REG 32
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#define MMAP_SAVE_AND_CONFIG 0
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#define MMAP_RESTORE_SAVED 1
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#define MMAP_SAVE_AND_CONFIG 0
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#define MMAP_RESTORE_SAVED 1
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/* SAR clock settings */
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#define MVEBU_AP_GEN_MGMT_BASE (MVEBU_RFU_BASE + 0x8000)
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@ -77,22 +78,17 @@
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(0x2c2 << 3) | \
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(0x1 << AVS_SOFT_RESET_OFFSET) | \
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(0x1 << AVS_ENABLE_OFFSET))
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/* VDD is 0.88V for 2GHz clock */
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#define AVS_A3900_HIGH_CLK_VALUE ((0x80 << 24) | \
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(0x2f5 << 13) | \
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(0x2f5 << 3) | \
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(0x1 << AVS_SOFT_RESET_OFFSET) | \
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(0x1 << AVS_ENABLE_OFFSET))
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#define MVEBU_AP_EFUSE_SRV_CTRL_REG (MVEBU_AP_GEN_MGMT_BASE + 0x8)
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#define EFUSE_SRV_CTRL_LD_SELECT_OFFS 6
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#define EFUSE_SRV_CTRL_LD_SEL_USER_MASK (1 << EFUSE_SRV_CTRL_LD_SELECT_OFFS)
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/* Notify bootloader on DRAM setup */
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#define AP807_CPU_ARO_0_CTRL_0 (MVEBU_RFU_BASE + 0x82A8)
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#define AP807_CPU_ARO_1_CTRL_0 (MVEBU_RFU_BASE + 0x8D00)
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/* 0 - ARO clock is enabled, 1 - ARO clock is disabled */
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#define AP807_CPU_ARO_CLK_EN_OFFSET 0
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#define AP807_CPU_ARO_CLK_EN_MASK (0x1 << AP807_CPU_ARO_CLK_EN_OFFSET)
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/* 0 - ARO is the clock source, 1 - PLL is the clock source */
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#define AP807_CPU_ARO_SEL_PLL_OFFSET 5
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#define AP807_CPU_ARO_SEL_PLL_MASK (0x1 << AP807_CPU_ARO_SEL_PLL_OFFSET)
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/*
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* - Identification information in the LD-0 eFuse:
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@ -143,9 +139,9 @@
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#define EFUSE_AP_LD0_WP_MASK 0x3FF
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#endif
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#define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
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#define EFUSE_AP_LD0_SVC4_OFFS 42 /* LD0[112:105] */
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#define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4
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#define EFUSE_AP_LD0_CLUSTER_DOWN_OFFS 4
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/* Return the AP revision of the chip */
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static unsigned int ble_get_ap_type(void)
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@ -207,37 +203,44 @@ static void ble_plat_mmap_config(int restore)
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*/
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static void ble_plat_avs_config(void)
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{
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uint32_t reg_val, device_id;
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uint32_t freq_mode, device_id;
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uint32_t avs_val = 0;
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freq_mode =
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SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE(
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FREQ_MODE_AP_SAR_REG_NUM)));
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/* Check which SoC is running and act accordingly */
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if (ble_get_ap_type() == CHIP_ID_AP807) {
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VERBOSE("AVS: Setting AP807 AVS CTRL to 0x%x\n",
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AVS_A3900_CLK_VALUE);
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mmio_write_32(AVS_EN_CTRL_REG, AVS_A3900_CLK_VALUE);
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return;
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/* Increase CPU voltage for higher CPU clock */
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if (freq_mode == CPU_2000_DDR_1200_RCLK_1200)
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avs_val = AVS_A3900_HIGH_CLK_VALUE;
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else
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avs_val = AVS_A3900_CLK_VALUE;
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} else {
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/* Check which SoC is running and act accordingly */
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device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
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switch (device_id) {
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case MVEBU_80X0_DEV_ID:
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case MVEBU_80X0_CP115_DEV_ID:
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/* Always fix the default AVS value on A80x0 */
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avs_val = AVS_A8K_CLK_VALUE;
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break;
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case MVEBU_70X0_DEV_ID:
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case MVEBU_70X0_CP115_DEV_ID:
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/* Fix AVS for CPU clocks lower than 1600MHz on A70x0 */
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if ((freq_mode > CPU_1600_DDR_900_RCLK_900_2) &&
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(freq_mode < CPU_DDR_RCLK_INVALID))
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avs_val = AVS_A7K_LOW_CLK_VALUE;
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break;
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default:
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ERROR("Unsupported Device ID 0x%x\n", device_id);
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return;
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}
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}
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/* Check which SoC is running and act accordingly */
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device_id = cp110_device_id_get(MVEBU_CP_REGS_BASE(0));
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switch (device_id) {
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case MVEBU_80X0_DEV_ID:
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case MVEBU_80X0_CP115_DEV_ID:
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/* Set the new AVS value - fix the default one on A80x0 */
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mmio_write_32(AVS_EN_CTRL_REG, AVS_A8K_CLK_VALUE);
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break;
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case MVEBU_70X0_DEV_ID:
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case MVEBU_70X0_CP115_DEV_ID:
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/* Only fix AVS for CPU clocks lower than 1600MHz on A70x0 */
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reg_val = mmio_read_32(MVEBU_AP_SAR_REG_BASE(
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FREQ_MODE_AP_SAR_REG_NUM));
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reg_val &= SAR_CLOCK_FREQ_MODE_MASK;
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reg_val >>= SAR_CLOCK_FREQ_MODE_OFFSET;
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if ((reg_val > CPU_1600_DDR_900_RCLK_900_2) &&
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(reg_val < CPU_DDR_RCLK_INVALID))
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mmio_write_32(AVS_EN_CTRL_REG, AVS_A7K_LOW_CLK_VALUE);
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break;
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default:
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ERROR("Unsupported Device ID 0x%x\n", device_id);
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if (avs_val) {
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VERBOSE("AVS: Setting AVS CTRL to 0x%x\n", avs_val);
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mmio_write_32(AVS_EN_CTRL_REG, avs_val);
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}
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}
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@ -543,35 +546,11 @@ static int ble_skip_current_image(void)
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}
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#endif
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/* Switch to ARO from PLL in ap807 */
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static void aro_to_pll(void)
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{
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unsigned int reg;
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/* switch from ARO to PLL */
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reg = mmio_read_32(AP807_CPU_ARO_0_CTRL_0);
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reg |= AP807_CPU_ARO_SEL_PLL_MASK;
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mmio_write_32(AP807_CPU_ARO_0_CTRL_0, reg);
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reg = mmio_read_32(AP807_CPU_ARO_1_CTRL_0);
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reg |= AP807_CPU_ARO_SEL_PLL_MASK;
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mmio_write_32(AP807_CPU_ARO_1_CTRL_0, reg);
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mdelay(1000);
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/* disable ARO clk driver */
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reg = mmio_read_32(AP807_CPU_ARO_0_CTRL_0);
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reg |= (AP807_CPU_ARO_CLK_EN_MASK);
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mmio_write_32(AP807_CPU_ARO_0_CTRL_0, reg);
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reg = mmio_read_32(AP807_CPU_ARO_1_CTRL_0);
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reg |= (AP807_CPU_ARO_CLK_EN_MASK);
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mmio_write_32(AP807_CPU_ARO_1_CTRL_0, reg);
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}
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int ble_plat_setup(int *skip)
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{
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int ret;
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unsigned int freq_mode;
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/* Power down unused CPUs */
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plat_marvell_early_cpu_powerdown();
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@ -598,9 +577,14 @@ int ble_plat_setup(int *skip)
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/* Setup AVS */
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ble_plat_svc_config();
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/* read clk option from sampled-at-reset register */
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freq_mode =
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SAR_CLOCK_FREQ_MODE(mmio_read_32(MVEBU_AP_SAR_REG_BASE(
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FREQ_MODE_AP_SAR_REG_NUM)));
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/* work with PLL clock driver in AP807 */
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if (ble_get_ap_type() == CHIP_ID_AP807)
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aro_to_pll();
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ap807_clocks_init(freq_mode);
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/* Do required AP setups for BLE stage */
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ap_ble_init();
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