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Merge "fix(versal-net): add default values for silicon" into integration

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Joanna Farley 2022-11-09 12:49:28 +01:00 • committed by TrustedFirmware Code Review
commit 0d231b9bdf
1 changed files with 3 additions and 0 deletions
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3
plat/xilinx/versal_net/bl31_versal_net_setup.c
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@ -88,6 +88,9 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
uart_clock = 25000000;
break;
case VERSAL_NET_SILICON:
cpu_clock = 100000000;
uart_clock = 100000000;
break;
default:
panic();
}