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https://github.com/ARM-software/arm-trusted-firmware.git
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Merge changes from topic "st-bsec3" into integration
* changes: feat(stm32mp2): add BSEC and OTP support feat(st-bsec): add driver for the new IP version BSEC3
This commit is contained in:
Manish Pandey
TrustedFirmware Code Review
commit
0d136806ed
5 changed files with 735 additions and 1 deletions
533
drivers/st/bsec/bsec3.c
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533
drivers/st/bsec/bsec3.c
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@ -0,0 +1,533 @@
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/*
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* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <limits.h>
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <drivers/st/bsec.h>
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#include <drivers/st/bsec3_reg.h>
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#include <drivers/st/stm32mp_reset.h>
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#include <lib/mmio.h>
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#include <lib/spinlock.h>
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#include <libfdt.h>
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#include <platform_def.h>
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#define BSEC_IP_VERSION_1_0 U(0x10)
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#define BSEC_IP_ID_3 U(0x100033)
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#define MAX_NB_TRIES U(3)
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/*
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* IP configuration
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*/
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#define BSEC_OTP_MASK GENMASK_32(4, 0)
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#define BSEC_OTP_BANK_SHIFT U(5)
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#define BSEC_TIMEOUT_VALUE U(0x800000) /* ~7sec @1.2GHz */
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/* Magic use to indicated valid SHADOW = 'B' 'S' 'E' 'C' */
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#define BSEC_MAGIC U(0x42534543)
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#define OTP_MAX_SIZE (STM32MP2_OTP_MAX_ID + U(1))
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struct bsec_shadow {
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uint32_t magic;
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uint32_t state;
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uint32_t value[OTP_MAX_SIZE];
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uint32_t status[OTP_MAX_SIZE];
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};
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static uint32_t otp_bank(uint32_t otp)
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{
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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return (otp & ~BSEC_OTP_MASK) >> BSEC_OTP_BANK_SHIFT;
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}
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static uint32_t otp_bit_mask(uint32_t otp)
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{
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return BIT(otp & BSEC_OTP_MASK);
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}
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/*
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* bsec_get_status: return status register value.
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*/
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static uint32_t bsec_get_status(void)
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{
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return mmio_read_32(BSEC_BASE + BSEC_OTPSR);
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}
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/*
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* bsec_get_version: return BSEC version.
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*/
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static uint32_t bsec_get_version(void)
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{
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return mmio_read_32(BSEC_BASE + BSEC_VERR) & BSEC_VERR_MASK;
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}
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/*
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* bsec_get_id: return BSEC ID.
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*/
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static uint32_t bsec_get_id(void)
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{
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return mmio_read_32(BSEC_BASE + BSEC_IPIDR);
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}
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static bool is_fuse_shadowed(uint32_t otp)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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uint32_t bank_value;
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bank_value = mmio_read_32(BSEC_BASE + BSEC_SFSR(bank));
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if ((bank_value & otp_mask) != 0U) {
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return true;
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}
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return false;
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}
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static void poll_otp_status_busy(void)
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{
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uint32_t timeout = BSEC_TIMEOUT_VALUE;
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while (((bsec_get_status() & BSEC_OTPSR_BUSY) != 0U) && (timeout != 0U)) {
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timeout--;
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}
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if ((bsec_get_status() & BSEC_OTPSR_BUSY) != 0U) {
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ERROR("BSEC timeout\n");
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panic();
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}
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}
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static uint32_t check_read_error(uint32_t otp)
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{
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uint32_t status = bsec_get_status();
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if ((status & BSEC_OTPSR_SECF) != 0U) {
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VERBOSE("BSEC read %u single error correction detected\n", otp);
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}
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if ((status & BSEC_OTPSR_PPLF) != 0U) {
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VERBOSE("BSEC read %u permanent programming lock detected.\n", otp);
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}
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if ((status & BSEC_OTPSR_PPLMF) != 0U) {
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ERROR("BSEC read %u error 0x%x\n", otp, status);
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return BSEC_ERROR;
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}
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if ((status & (BSEC_OTPSR_DISTURBF | BSEC_OTPSR_DEDF | BSEC_OTPSR_AMEF)) != 0U) {
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ERROR("BSEC read %u error 0x%x with invalid FVR\n", otp, status);
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return BSEC_RETRY;
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}
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return BSEC_OK;
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}
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static uint32_t check_program_error(uint32_t otp)
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{
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uint32_t status = bsec_get_status();
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if ((status & BSEC_OTPSR_PROGFAIL) != 0U) {
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ERROR("BSEC program %u error 0x%x\n", otp, status);
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return BSEC_RETRY;
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}
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return BSEC_OK;
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}
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static void check_reset_error(void)
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{
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uint32_t status = bsec_get_status();
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/* check initial status reporting */
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if ((status & BSEC_OTPSR_BUSY) != 0U) {
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VERBOSE("BSEC reset and busy when OTPSR read\n");
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}
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if ((status & BSEC_OTPSR_HIDEUP) != 0U) {
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VERBOSE("BSEC upper fuse are not accessible (HIDEUP)\n");
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}
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if ((status & BSEC_OTPSR_OTPSEC) != 0U) {
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VERBOSE("BSEC reset single error correction detected\n");
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}
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if ((status & BSEC_OTPSR_OTPNVIR) == 0U) {
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VERBOSE("BSEC reset first fuse word 0 is detected zero\n");
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}
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if ((status & BSEC_OTPSR_OTPERR) != 0U) {
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ERROR("BSEC reset critical error 0x%x\n", status);
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panic();
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}
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if ((status & BSEC_OTPSR_FUSEOK) != BSEC_OTPSR_FUSEOK) {
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ERROR("BSEC reset critical error 0x%x\n", status);
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panic();
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}
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}
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static bool is_bsec_write_locked(void)
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{
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return (mmio_read_32(BSEC_BASE + BSEC_LOCKR) & BSEC_LOCKR_GWLOCK_MASK) != 0U;
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}
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/*
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* bsec_probe: initialize BSEC driver.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_probe(void)
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{
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uint32_t version = bsec_get_version();
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uint32_t id = bsec_get_id();
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if ((version != BSEC_IP_VERSION_1_0) || (id != BSEC_IP_ID_3)) {
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ERROR("%s: version = 0x%x, id = 0x%x\n", __func__, version, id);
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panic();
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}
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check_reset_error();
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return BSEC_OK;
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}
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/*
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* bsec_shadow_register: copy SAFMEM OTP to BSEC data.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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static uint32_t bsec_shadow_register(uint32_t otp)
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{
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uint32_t result;
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uint32_t i;
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bool value;
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result = bsec_read_sr_lock(otp, &value);
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if (result != BSEC_OK) {
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WARN("BSEC: %u Sticky-read bit read Error %u\n", otp, result);
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} else if (value) {
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VERBOSE("BSEC: OTP %u is locked and will not be refreshed\n", otp);
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}
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for (i = 0U; i < MAX_NB_TRIES; i++) {
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mmio_write_32(BSEC_BASE + BSEC_OTPCR, otp);
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poll_otp_status_busy();
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result = check_read_error(otp);
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if (result != BSEC_RETRY) {
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break;
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}
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}
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return result;
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}
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/*
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* bsec_write_otp: write a value in shadow OTP.
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* val: value to program.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_write_otp(uint32_t val, uint32_t otp)
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{
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bool state;
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uint32_t result;
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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if (!is_fuse_shadowed(otp)) {
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return BSEC_ERROR;
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}
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if (is_bsec_write_locked()) {
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return BSEC_WRITE_LOCKED;
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}
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result = bsec_read_sw_lock(otp, &state);
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if (result != BSEC_OK) {
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WARN("Shadow register is SW locked\n");
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return result;
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}
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mmio_write_32(BSEC_BASE + BSEC_FVR(otp), val);
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return BSEC_OK;
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}
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/*
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* bsec_program_otp: program a bit in SAFMEM after the prog.
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* The OTP data is not refreshed.
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* val: value to program.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_program_otp(uint32_t val, uint32_t otp)
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{
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uint32_t result;
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uint32_t i;
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bool value;
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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if (is_bsec_write_locked() == true) {
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return BSEC_WRITE_LOCKED;
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}
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result = bsec_read_sp_lock(otp, &value);
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if (result != BSEC_OK) {
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WARN("BSEC: %u Sticky-prog bit read Error %u\n", otp, result);
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} else if (value) {
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WARN("BSEC: OTP locked, prog will be ignored\n");
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return BSEC_WRITE_LOCKED;
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}
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mmio_write_32(BSEC_BASE + BSEC_WDR, val);
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for (i = 0U; i < MAX_NB_TRIES; i++) {
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mmio_write_32(BSEC_BASE + BSEC_OTPCR, otp | BSEC_OTPCR_PROG);
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poll_otp_status_busy();
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result = check_program_error(otp);
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if (result != BSEC_RETRY) {
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break;
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}
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}
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return result;
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}
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/*
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* bsec_read_debug_conf: read debug configuration.
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*/
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uint32_t bsec_read_debug_conf(void)
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{
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return mmio_read_32(BSEC_BASE + BSEC_DENR);
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}
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static uint32_t bsec_lock_register_set(uint32_t offset, uint32_t mask)
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{
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uint32_t value = mmio_read_32(BSEC_BASE + offset);
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/* The lock is already set */
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if ((value & mask) != 0U) {
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return BSEC_OK;
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}
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if (is_bsec_write_locked()) {
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return BSEC_WRITE_LOCKED;
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}
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value |= mask;
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mmio_write_32(BSEC_BASE + offset, value);
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return BSEC_OK;
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}
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static bool bsec_lock_register_get(uint32_t offset, uint32_t mask)
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{
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uint32_t value = mmio_read_32(BSEC_BASE + offset);
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return (value & mask) != 0U;
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}
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/*
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* bsec_set_sr_lock: set shadow-read lock.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_set_sr_lock(uint32_t otp)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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return bsec_lock_register_set(BSEC_SRLOCK(bank), otp_mask);
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}
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/*
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* bsec_read_sr_lock: read shadow-read lock.
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* otp: OTP number.
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* value: read value (true or false).
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_read_sr_lock(uint32_t otp, bool *value)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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assert(value != NULL);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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*value = bsec_lock_register_get(BSEC_SRLOCK(bank), otp_mask);
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return BSEC_OK;
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}
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/*
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* bsec_set_sw_lock: set shadow-write lock.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_set_sw_lock(uint32_t otp)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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return bsec_lock_register_set(BSEC_SWLOCK(bank), otp_mask);
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}
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/*
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* bsec_read_sw_lock: read shadow-write lock.
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* otp: OTP number.
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* value: read value (true or false).
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_read_sw_lock(uint32_t otp, bool *value)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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assert(value != NULL);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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*value = bsec_lock_register_get(BSEC_SWLOCK(bank), otp_mask);
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return BSEC_OK;
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}
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/*
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* bsec_set_sp_lock: set shadow-program lock.
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* otp: OTP number.
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_set_sp_lock(uint32_t otp)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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return bsec_lock_register_set(BSEC_SPLOCK(bank), otp_mask);
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}
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/*
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* bsec_read_sp_lock: read shadow-program lock.
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* otp: OTP number.
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* value: read value (true or false).
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* return value: BSEC_OK if no error.
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*/
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uint32_t bsec_read_sp_lock(uint32_t otp, bool *value)
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{
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uint32_t bank = otp_bank(otp);
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uint32_t otp_mask = otp_bit_mask(otp);
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assert(value != NULL);
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if (otp > STM32MP2_OTP_MAX_ID) {
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panic();
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}
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*value = bsec_lock_register_get(BSEC_SPLOCK(bank), otp_mask);
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return BSEC_OK;
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}
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/*
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* bsec_get_secure_state: read state in BSEC status register.
|
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* return: secure state
|
||||
*/
|
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uint32_t bsec_get_secure_state(void)
|
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{
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uint32_t state = BSEC_STATE_INVALID;
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uint32_t status = bsec_get_status();
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uint32_t bsec_sr = mmio_read_32(BSEC_BASE + BSEC_SR);
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if ((status & BSEC_OTPSR_FUSEOK) == BSEC_OTPSR_FUSEOK) {
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/* NVSTATE is only valid if FUSEOK */
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uint32_t nvstates = (bsec_sr & BSEC_SR_NVSTATE_MASK) >> BSEC_SR_NVSTATE_SHIFT;
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if (nvstates == BSEC_SR_NVSTATE_OPEN) {
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state = BSEC_STATE_SEC_OPEN;
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} else if (nvstates == BSEC_SR_NVSTATE_CLOSED) {
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state = BSEC_STATE_SEC_CLOSED;
|
||||
} else {
|
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VERBOSE("%s nvstates = %u\n", __func__, nvstates);
|
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}
|
||||
}
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return state;
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}
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||||
|
||||
/*
|
||||
* bsec_shadow_read_otp: Load OTP from SAFMEM and provide its value
|
||||
* val: read value.
|
||||
* otp: OTP number.
|
||||
* return value: BSEC_OK if no error.
|
||||
*/
|
||||
uint32_t bsec_shadow_read_otp(uint32_t *val, uint32_t otp)
|
||||
{
|
||||
assert(val != NULL);
|
||||
if (otp > STM32MP2_OTP_MAX_ID) {
|
||||
panic();
|
||||
}
|
||||
|
||||
*val = 0U;
|
||||
|
||||
if (is_bsec_write_locked()) {
|
||||
return BSEC_WRITE_LOCKED;
|
||||
}
|
||||
|
||||
if (!is_fuse_shadowed(otp)) {
|
||||
uint32_t result = bsec_shadow_register(otp);
|
||||
|
||||
if (result != BSEC_OK) {
|
||||
ERROR("BSEC: %u Shadowing Error %u\n", otp, result);
|
||||
return result;
|
||||
}
|
||||
}
|
||||
|
||||
*val = mmio_read_32(BSEC_BASE + BSEC_FVR(otp));
|
||||
|
||||
return BSEC_OK;
|
||||
}
|
||||
|
||||
/*
|
||||
* bsec_read_otp: read an OTP data value.
|
||||
* val: read value.
|
||||
* otp: OTP number.
|
||||
* return value: BSEC_OK if no error.
|
||||
*/
|
||||
uint32_t bsec_read_otp(uint32_t *val, uint32_t otp)
|
||||
{
|
||||
assert(val != NULL);
|
||||
if (otp > STM32MP2_OTP_MAX_ID) {
|
||||
panic();
|
||||
}
|
||||
|
||||
return bsec_shadow_read_otp(val, otp);
|
||||
}
|
||||
103
include/drivers/st/bsec3_reg.h
Normal file
103
include/drivers/st/bsec3_reg.h
Normal file
|
|
@ -0,0 +1,103 @@
|
|||
/*
|
||||
* Copyright (c) 2024, STMicroelectronics - All Rights Reserved
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef BSEC3_REG_H
|
||||
#define BSEC3_REG_H
|
||||
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
/* BSEC REGISTER OFFSET (base relative) */
|
||||
#define BSEC_FVR(x) (U(0x000) + 4U * (x))
|
||||
#define BSEC_SPLOCK(x) (U(0x800) + 4U * (x))
|
||||
#define BSEC_SWLOCK(x) (U(0x840) + 4U * (x))
|
||||
#define BSEC_SRLOCK(x) (U(0x880) + 4U * (x))
|
||||
#define BSEC_OTPVLDR(x) (U(0x8C0) + 4U * (x))
|
||||
#define BSEC_SFSR(x) (U(0x940) + 4U * (x))
|
||||
#define BSEC_OTPCR U(0xC04)
|
||||
#define BSEC_WDR U(0xC08)
|
||||
#define BSEC_SCRATCHR0 U(0xE00)
|
||||
#define BSEC_SCRATCHR1 U(0xE04)
|
||||
#define BSEC_SCRATCHR2 U(0xE08)
|
||||
#define BSEC_SCRATCHR3 U(0xE0C)
|
||||
#define BSEC_LOCKR U(0xE10)
|
||||
#define BSEC_JTAGINR U(0xE14)
|
||||
#define BSEC_JTAGOUTR U(0xE18)
|
||||
#define BSEC_DENR U(0xE20)
|
||||
#define BSEC_UNMAPR U(0xE24)
|
||||
#define BSEC_SR U(0xE40)
|
||||
#define BSEC_OTPSR U(0xE44)
|
||||
#define BSEC_WRCR U(0xF00)
|
||||
#define BSEC_HWCFGR U(0xFF0)
|
||||
#define BSEC_VERR U(0xFF4)
|
||||
#define BSEC_IPIDR U(0xFF8)
|
||||
#define BSEC_SIDR U(0xFFC)
|
||||
|
||||
/* BSEC_OTPCR register fields */
|
||||
#define BSEC_OTPCR_ADDR_MASK GENMASK_32(8, 0)
|
||||
#define BSEC_OTPCR_ADDR_SHIFT U(0)
|
||||
#define BSEC_OTPCR_PROG BIT_32(13)
|
||||
#define BSEC_OTPCR_PPLOCK BIT_32(14)
|
||||
#define BSEC_OTPCR_LASTCID_MASK GENMASK_32(21, 19)
|
||||
#define BSEC_OTPCR_LASTCID_SHIFT U(19)
|
||||
|
||||
/* BSEC_LOCKR register fields */
|
||||
#define BSEC_LOCKR_GWLOCK_MASK BIT_32(0)
|
||||
#define BSEC_LOCKR_GWLOCK_SHIFT U(0)
|
||||
#define BSEC_LOCKR_DENLOCK_MASK BIT_32(1)
|
||||
#define BSEC_LOCKR_DENLOCK_SHIFT U(1)
|
||||
#define BSEC_LOCKR_HKLOCK_MASK BIT_32(2)
|
||||
#define BSEC_LOCKR_HKLOCK_SHIFT U(2)
|
||||
|
||||
/* BSEC_DENR register fields */
|
||||
#define BSEC_DENR_LPDBGEN BIT_32(0)
|
||||
#define BSEC_DENR_DBGENA BIT_32(1)
|
||||
#define BSEC_DENR_NIDENA BIT_32(2)
|
||||
#define BSEC_DENR_DEVICEEN BIT_32(3)
|
||||
#define BSEC_DENR_HDPEN BIT_32(4)
|
||||
#define BSEC_DENR_SPIDENA BIT_32(5)
|
||||
#define BSEC_DENR_SPNIDENA BIT_32(6)
|
||||
#define BSEC_DENR_DBGSWEN BIT_32(7)
|
||||
#define BSEC_DENR_DBGENM BIT_32(8)
|
||||
#define BSEC_DENR_NIDENM BIT_32(9)
|
||||
#define BSEC_DENR_SPIDENM BIT_32(10)
|
||||
#define BSEC_DENR_SPNIDENM BIT_32(11)
|
||||
#define BSEC_DENR_CFGSDIS BIT_32(12)
|
||||
#define BSEC_DENR_CP15SDIS_MASK GENMASK_32(14, 13)
|
||||
#define BSEC_DENR_CP15SDIS_SHIFT U(13)
|
||||
#define BSEC_DENR_LPDBGDIS BIT_32(15)
|
||||
#define BSEC_DENR_ALL_MSK GENMASK_32(15, 0)
|
||||
|
||||
/* BSEC_SR register fields */
|
||||
#define BSEC_SR_BUSY BIT_32(0)
|
||||
#define BSEC_SR_HVALID BIT_32(1)
|
||||
#define BSEC_SR_RNGERR BIT_32(2)
|
||||
#define BSEC_SR_HKWW_MASK GENMASK_32(15, 8)
|
||||
#define BSEC_SR_HKWW_SHIFT U(8)
|
||||
#define BSEC_SR_NVSTATE_MASK GENMASK_32(31, 26)
|
||||
#define BSEC_SR_NVSTATE_SHIFT U(26)
|
||||
#define BSEC_SR_NVSTATE_OPEN U(0x16)
|
||||
#define BSEC_SR_NVSTATE_CLOSED U(0x0D)
|
||||
#define BSEC_SR_NVSTATE_OTP_LOCKED U(0x23)
|
||||
|
||||
/* BSEC_OTPSR register fields */
|
||||
#define BSEC_OTPSR_BUSY BIT_32(0)
|
||||
#define BSEC_OTPSR_FUSEOK BIT_32(1)
|
||||
#define BSEC_OTPSR_HIDEUP BIT_32(2)
|
||||
#define BSEC_OTPSR_OTPNVIR BIT_32(4)
|
||||
#define BSEC_OTPSR_OTPERR BIT_32(5)
|
||||
#define BSEC_OTPSR_OTPSEC BIT_32(6)
|
||||
#define BSEC_OTPSR_PROGFAIL BIT_32(16)
|
||||
#define BSEC_OTPSR_DISTURBF BIT_32(17)
|
||||
#define BSEC_OTPSR_DEDF BIT_32(18)
|
||||
#define BSEC_OTPSR_SECF BIT_32(19)
|
||||
#define BSEC_OTPSR_PPLF BIT_32(20)
|
||||
#define BSEC_OTPSR_PPLMF BIT_32(21)
|
||||
#define BSEC_OTPSR_AMEF BIT_32(22)
|
||||
|
||||
/* BSEC_VERR register fields */
|
||||
#define BSEC_VERR_MASK GENMASK_32(7, 0)
|
||||
|
||||
#endif /* BSEC3_REG_H */
|
||||
|
|
@ -7,8 +7,10 @@
|
|||
#include <cdefs.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <plat/common/platform.h>
|
||||
|
||||
#include <platform_def.h>
|
||||
#include <stm32mp_common.h>
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg0 __unused,
|
||||
|
|
@ -25,4 +27,8 @@ void bl2_platform_setup(void)
|
|||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
if (stm32_otp_probe() != 0U) {
|
||||
ERROR("OTP probe failed\n");
|
||||
panic();
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
#
|
||||
# Copyright (c) 2023, STMicroelectronics - All Rights Reserved
|
||||
# Copyright (c) 2023-2024, STMicroelectronics - All Rights Reserved
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
|
@ -46,6 +46,8 @@ PLAT_BL_COMMON_SOURCES += lib/cpus/${ARCH}/cortex_a35.S
|
|||
PLAT_BL_COMMON_SOURCES += drivers/st/uart/${ARCH}/stm32_console.S
|
||||
PLAT_BL_COMMON_SOURCES += plat/st/stm32mp2/${ARCH}/stm32mp2_helper.S
|
||||
|
||||
PLAT_BL_COMMON_SOURCES += drivers/st/bsec/bsec3.c
|
||||
|
||||
BL2_SOURCES += plat/st/stm32mp2/plat_bl2_mem_params_desc.c
|
||||
BL2_SOURCES += plat/st/stm32mp2/bl2_plat_setup.c
|
||||
|
||||
|
|
|
|||
|
|
@ -157,6 +157,96 @@ enum ddr_type {
|
|||
#define STM32MP_SDMMC2_BASE U(0x48230000)
|
||||
#define STM32MP_SDMMC3_BASE U(0x48240000)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 BSEC / OTP
|
||||
******************************************************************************/
|
||||
/*
|
||||
* 367 available OTPs, the other are masked
|
||||
* - ECIES key: 368 to 375 (only readable by bootrom)
|
||||
* - HWKEY: 376 to 383 (never reloadable or readable)
|
||||
*/
|
||||
#define STM32MP2_OTP_MAX_ID U(0x16F)
|
||||
#define STM32MP2_MID_OTP_START U(0x80)
|
||||
#define STM32MP2_UPPER_OTP_START U(0x100)
|
||||
|
||||
/* OTP labels */
|
||||
#define PART_NUMBER_OTP "part-number-otp"
|
||||
#define PACKAGE_OTP "package-otp"
|
||||
#define HCONF1_OTP "otp124"
|
||||
#define NAND_OTP "otp16"
|
||||
#define NAND2_OTP "otp20"
|
||||
#define BOARD_ID_OTP "board-id"
|
||||
#define UID_OTP "uid-otp"
|
||||
#define LIFECYCLE2_OTP "otp18"
|
||||
#define PKH_OTP "otp144"
|
||||
#define ENCKEY_OTP "otp260"
|
||||
|
||||
/* OTP mask */
|
||||
/* PACKAGE */
|
||||
#define PACKAGE_OTP_PKG_MASK GENMASK_32(2, 0)
|
||||
#define PACKAGE_OTP_PKG_SHIFT U(0)
|
||||
|
||||
/* IWDG OTP */
|
||||
#define HCONF1_OTP_IWDG_HW_POS U(0)
|
||||
#define HCONF1_OTP_IWDG_FZ_STOP_POS U(1)
|
||||
#define HCONF1_OTP_IWDG_FZ_STANDBY_POS U(2)
|
||||
|
||||
/* NAND OTP */
|
||||
/* NAND parameter storage flag */
|
||||
#define NAND_PARAM_STORED_IN_OTP BIT_32(31)
|
||||
|
||||
/* NAND page size in bytes */
|
||||
#define NAND_PAGE_SIZE_MASK GENMASK_32(30, 29)
|
||||
#define NAND_PAGE_SIZE_SHIFT U(29)
|
||||
#define NAND_PAGE_SIZE_2K U(0)
|
||||
#define NAND_PAGE_SIZE_4K U(1)
|
||||
#define NAND_PAGE_SIZE_8K U(2)
|
||||
|
||||
/* NAND block size in pages */
|
||||
#define NAND_BLOCK_SIZE_MASK GENMASK_32(28, 27)
|
||||
#define NAND_BLOCK_SIZE_SHIFT U(27)
|
||||
#define NAND_BLOCK_SIZE_64_PAGES U(0)
|
||||
#define NAND_BLOCK_SIZE_128_PAGES U(1)
|
||||
#define NAND_BLOCK_SIZE_256_PAGES U(2)
|
||||
|
||||
/* NAND number of block (in unit of 256 blocks) */
|
||||
#define NAND_BLOCK_NB_MASK GENMASK_32(26, 19)
|
||||
#define NAND_BLOCK_NB_SHIFT U(19)
|
||||
#define NAND_BLOCK_NB_UNIT U(256)
|
||||
|
||||
/* NAND bus width in bits */
|
||||
#define NAND_WIDTH_MASK BIT_32(18)
|
||||
#define NAND_WIDTH_SHIFT U(18)
|
||||
|
||||
/* NAND number of ECC bits per 512 bytes */
|
||||
#define NAND_ECC_BIT_NB_MASK GENMASK_32(17, 15)
|
||||
#define NAND_ECC_BIT_NB_SHIFT U(15)
|
||||
#define NAND_ECC_BIT_NB_UNSET U(0)
|
||||
#define NAND_ECC_BIT_NB_1_BITS U(1)
|
||||
#define NAND_ECC_BIT_NB_4_BITS U(2)
|
||||
#define NAND_ECC_BIT_NB_8_BITS U(3)
|
||||
#define NAND_ECC_ON_DIE U(4)
|
||||
|
||||
/* NAND number of planes */
|
||||
#define NAND_PLANE_BIT_NB_MASK BIT_32(14)
|
||||
|
||||
/* NAND2 OTP */
|
||||
#define NAND2_PAGE_SIZE_SHIFT U(16)
|
||||
|
||||
/* NAND2 config distribution */
|
||||
#define NAND2_CONFIG_DISTRIB BIT_32(0)
|
||||
#define NAND2_PNAND_NAND2_SNAND_NAND1 U(0)
|
||||
#define NAND2_PNAND_NAND1_SNAND_NAND2 U(1)
|
||||
|
||||
/* MONOTONIC OTP */
|
||||
#define MAX_MONOTONIC_VALUE U(32)
|
||||
|
||||
/* UID OTP */
|
||||
#define UID_WORD_NB U(3)
|
||||
|
||||
/* Lifecycle OTP */
|
||||
#define SECURE_BOOT_CLOSED_SECURE GENMASK_32(3, 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* STM32MP2 TAMP
|
||||
******************************************************************************/
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue