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fix(layerscape): unlock write access SMMU_CBn_ACTLR

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This patch is to fix Errata #841119 and #826419 failed apply in linux
because of SMMU_CBn_ACTLR register can't be modified in non-secure
states.

Signed-off-by: Howard Lu <howard.lu@nxp.com>
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Change-Id: I2b23e7c8baa809f385917eb45b10ec6b26a9ada8
This commit is contained in:
Howard Lu 2022-11-01 19:45:46 +08:00 • committed by Jiafei Pan
parent e83812f11a
commit 0ca1d8fba3
9 changed files with 40 additions and 12 deletions
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12
include/drivers/nxp/smmu/nxp_smmu.h
View file

@ -10,10 +10,13 @@
#define SMMU_SCR0 (0x0) #define SMMU_SCR0 (0x0)
#define SMMU_NSCR0 (0x400) #define SMMU_NSCR0 (0x400)
#define SMMU_SACR (0x10)
#define SCR0_CLIENTPD_MASK 0x00000001 #define SCR0_CLIENTPD_MASK 0x00000001
#define SCR0_USFCFG_MASK 0x00000400 #define SCR0_USFCFG_MASK 0x00000400
#define SMMU_SACR_CACHE_LOCK_ENABLE_BIT (1ULL << 26U)
static inline void bypass_smmu(uintptr_t smmu_base_addr) static inline void bypass_smmu(uintptr_t smmu_base_addr)
{ {
uint32_t val; uint32_t val;
@ -27,4 +30,13 @@ static inline void bypass_smmu(uintptr_t smmu_base_addr)
mmio_write_32((smmu_base_addr + SMMU_NSCR0), val); mmio_write_32((smmu_base_addr + SMMU_NSCR0), val);
} }
static inline void smmu_cache_unlock(uintptr_t smmu_base_addr)
{
uint32_t val;
val = mmio_read_32((smmu_base_addr + SMMU_SACR));
val &= (uint32_t)~SMMU_SACR_CACHE_LOCK_ENABLE_BIT;
mmio_write_32((smmu_base_addr + SMMU_SACR), val);
}
#endif #endif

8
plat/nxp/soc-ls1043a/soc.c
View file

@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION #ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h> #include <nxp_gpio.h>
#endif #endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h> #include <nxp_smmu.h>
#endif
#include <nxp_timer.h> #include <nxp_timer.h>
#include <plat_console.h> #include <plat_console.h>
#include <plat_gic.h> #include <plat_gic.h>
@ -174,6 +172,12 @@ void soc_early_init(void)
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters); plat_ls_interconnect_enter_coherency(num_clusters);
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
uint32_t mode; uint32_t mode;

2
plat/nxp/soc-ls1043a/soc.mk
View file

@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features # For Security Features
DISABLE_FUSE_WRITE := 1 DISABLE_FUSE_WRITE := 1
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes SECURE_BOOT := yes

8
plat/nxp/soc-ls1046a/soc.c
View file

@ -21,9 +21,7 @@
#ifdef POLICY_FUSE_PROVISION #ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h> #include <nxp_gpio.h>
#endif #endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h> #include <nxp_smmu.h>
#endif
#include <nxp_timer.h> #include <nxp_timer.h>
#include <plat_console.h> #include <plat_console.h>
#include <plat_gic.h> #include <plat_gic.h>
@ -168,6 +166,12 @@ void soc_early_init(void)
get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster); get_cluster_info(soc_list, ARRAY_SIZE(soc_list), &num_clusters, &cores_per_cluster);
plat_ls_interconnect_enter_coherency(num_clusters); plat_ls_interconnect_enter_coherency(num_clusters);
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
uint32_t mode; uint32_t mode;

2
plat/nxp/soc-ls1046a/soc.mk
View file

@ -19,8 +19,8 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features # For Security Features
DISABLE_FUSE_WRITE := 1 DISABLE_FUSE_WRITE := 1
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1)
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
SECURE_BOOT := yes SECURE_BOOT := yes

8
plat/nxp/soc-ls1088a/soc.c
View file

@ -17,9 +17,7 @@
#include <lib/mmio.h> #include <lib/mmio.h>
#include <lib/xlat_tables/xlat_tables_v2.h> #include <lib/xlat_tables/xlat_tables_v2.h>
#include <ls_interconnect.h> #include <ls_interconnect.h>
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h> #include <nxp_smmu.h>
#endif
#include <nxp_timer.h> #include <nxp_timer.h>
#include <plat_console.h> #include <plat_console.h>
#include <plat_gic.h> #include <plat_gic.h>
@ -254,6 +252,12 @@ void soc_early_init(void)
MT_DEVICE | MT_RW | MT_NS); MT_DEVICE | MT_RW | MT_NS);
} }
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
uint32_t mode; uint32_t mode;

2
plat/nxp/soc-ls1088a/soc.mk
View file

@ -23,12 +23,12 @@ include ${PLAT_COMMON_PATH}/plat_make_helper/plat_build_macros.mk
# For Security Features # For Security Features
DISABLE_FUSE_WRITE := 1 DISABLE_FUSE_WRITE := 1
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1) ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1) ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image # Save Keys to be used by DDR FIP image
SAVE_KEYS=1 SAVE_KEYS=1
endif endif
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to # Used by create_pbl tool to

8
plat/nxp/soc-lx2160a/soc.c
View file

@ -23,9 +23,7 @@
#ifdef POLICY_FUSE_PROVISION #ifdef POLICY_FUSE_PROVISION
#include <nxp_gpio.h> #include <nxp_gpio.h>
#endif #endif
#if TRUSTED_BOARD_BOOT
#include <nxp_smmu.h> #include <nxp_smmu.h>
#endif
#include <nxp_timer.h> #include <nxp_timer.h>
#include <plat_console.h> #include <plat_console.h>
#include <plat_gic.h> #include <plat_gic.h>
@ -286,6 +284,12 @@ void soc_early_init(void)
sfp_init(NXP_SFP_ADDR); sfp_init(NXP_SFP_ADDR);
#endif #endif
/*
* Unlock write access for SMMU SMMU_CBn_ACTLR in all Non-secure contexts.
*/
smmu_cache_unlock(NXP_SMMU_ADDR);
INFO("SMMU Cache Unlocking is Configured.\n");
#if TRUSTED_BOARD_BOOT #if TRUSTED_BOARD_BOOT
uint32_t mode; uint32_t mode;

2
plat/nxp/soc-lx2160a/soc.mk
View file

@ -36,12 +36,12 @@ endif
# For Security Features # For Security Features
DISABLE_FUSE_WRITE := 1 DISABLE_FUSE_WRITE := 1
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
ifeq (${TRUSTED_BOARD_BOOT}, 1) ifeq (${TRUSTED_BOARD_BOOT}, 1)
ifeq (${GENERATE_COT},1) ifeq (${GENERATE_COT},1)
# Save Keys to be used by DDR FIP image # Save Keys to be used by DDR FIP image
SAVE_KEYS=1 SAVE_KEYS=1
endif endif
$(eval $(call SET_NXP_MAKE_FLAG,SMMU_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SFP_NEEDED,BL2))
$(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2)) $(eval $(call SET_NXP_MAKE_FLAG,SNVS_NEEDED,BL2))
# Used by create_pbl tool to # Used by create_pbl tool to