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Add support for Cortex-A57 erratum 829520 workaround

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Change-Id: Ia2ce8aa752efb090cfc734c1895c8f2539e82439
This commit is contained in:
Sandrine Bailleux 2016-04-14 14:18:07 +01:00
parent a8b1c76936
commit 0b77197baf
4 changed files with 44 additions and 0 deletions
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3
docs/cpu-specific-build-macros.md
View file

@ -66,6 +66,9 @@ For Cortex-A57, following errata build flags are defined :
* `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57 * `ERRATA_A57_828024`: This applies errata 828024 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p1 of the CPU. CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
* `ERRATA_A57_829520`: This applies errata 829520 workaround to Cortex-A57
CPU. This needs to be enabled only for revision <= r1p2 of the CPU.
3. CPU Specific optimizations 3. CPU Specific optimizations
------------------------------ ------------------------------

1
include/lib/cpus/aarch64/cortex_a57.h
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@ -67,6 +67,7 @@
#define CPUACTLR_DCC_AS_DCCI (1 << 44) #define CPUACTLR_DCC_AS_DCCI (1 << 44)
#define CPUACTLR_DIS_STREAMING (3 << 27) #define CPUACTLR_DIS_STREAMING (3 << 27)
#define CPUACTLR_DIS_L1_STREAMING (3 << 25) #define CPUACTLR_DIS_L1_STREAMING (3 << 25)
#define CPUACTLR_DIS_INDIRECT_PREDICTOR (1 << 4)
/******************************************************************************* /*******************************************************************************
* L2 Control register specific definitions. * L2 Control register specific definitions.

32
lib/cpus/aarch64/cortex_a57.S
View file

@ -225,6 +225,32 @@ apply_828024:
ret ret
endfunc errata_a57_828024_wa endfunc errata_a57_828024_wa
/* ---------------------------------------------------
* Errata Workaround for Cortex A57 Errata #829520.
* This applies only to revision <= r1p2 of Cortex A57.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Clobbers : x0 - x5
* ---------------------------------------------------
*/
func errata_a57_829520_wa
/*
* Compare x0 against revision r1p2
*/
cmp x0, #0x12
b.ls apply_829520
#if LOG_LEVEL >= LOG_LEVEL_VERBOSE
b print_revision_warning
#else
ret
#endif
apply_829520:
mrs x1, CPUACTLR_EL1
orr x1, x1, #CPUACTLR_DIS_INDIRECT_PREDICTOR
msr CPUACTLR_EL1, x1
ret
endfunc errata_a57_829520_wa
/* ------------------------------------------------- /* -------------------------------------------------
* The CPU Ops reset function for Cortex-A57. * The CPU Ops reset function for Cortex-A57.
* Clobbers: x0-x5, x15, x19, x30 * Clobbers: x0-x5, x15, x19, x30
@ -267,6 +293,12 @@ func cortex_a57_reset_func
mov x0, x15 mov x0, x15
bl errata_a57_828024_wa bl errata_a57_828024_wa
#endif #endif
#if ERRATA_A57_829520
mov x0, x15
bl errata_a57_829520_wa
#endif
/* --------------------------------------------- /* ---------------------------------------------
* Enable the SMP bit. * Enable the SMP bit.
* --------------------------------------------- * ---------------------------------------------

8
lib/cpus/cpu-ops.mk
View file

@ -82,6 +82,10 @@ ERRATA_A57_826974 ?=0
# only to revision <= r1p1 of the Cortex A57 cpu. # only to revision <= r1p1 of the Cortex A57 cpu.
ERRATA_A57_828024 ?=0 ERRATA_A57_828024 ?=0
# Flag to apply erratum 829520 workaround during reset. This erratum applies
# only to revision <= r1p2 of the Cortex A57 cpu.
ERRATA_A57_829520 ?=0
# Process ERRATA_A53_826319 flag # Process ERRATA_A53_826319 flag
$(eval $(call assert_boolean,ERRATA_A53_826319)) $(eval $(call assert_boolean,ERRATA_A53_826319))
$(eval $(call add_define,ERRATA_A53_826319)) $(eval $(call add_define,ERRATA_A53_826319))
@ -105,3 +109,7 @@ $(eval $(call add_define,ERRATA_A57_826974))
# Process ERRATA_A57_828024 flag # Process ERRATA_A57_828024 flag
$(eval $(call assert_boolean,ERRATA_A57_828024)) $(eval $(call assert_boolean,ERRATA_A57_828024))
$(eval $(call add_define,ERRATA_A57_828024)) $(eval $(call add_define,ERRATA_A57_828024))
# Process ERRATA_A57_829520 flag
$(eval $(call assert_boolean,ERRATA_A57_829520))
$(eval $(call add_define,ERRATA_A57_829520))