mirror of
https://github.com/ARM-software/arm-trusted-firmware.git
synced 2025-04-16 09:34:18 +00:00
refactor(cpus): convert the Cortex-A77 to use the errata framework
This involves replacing:
* the reset_func with the standard cpu_reset_func_{start,end} to apply
errata automatically
* the <cpu>_errata_report with the errata_report_shim to report errata
automatically
...and for each erratum:
* the prologue with the workaround_<type>_start to do the checks and
framework registration automatically
* the epilogue with the workaround_<type>_end
* the checker function with the check_erratum_<type> to make it more
descriptive
It is important to note that the errata workaround sequences remain
unchanged and preserve their git blame.
Signed-off-by: Boyan Karatotev <boyan.karatotev@arm.com>
Change-Id: I5b74bf56eee95f54a1fb2fc6d3eccd86e26b522e
This commit is contained in:
Boyan Karatotev
Sona Mathew
parent
99787a4c0d
commit
0b3a4b5af8
1 changed files with 40 additions and 250 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2018-2022, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -26,26 +26,13 @@
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wa_cve_2022_23960_bhb_vector_table CORTEX_A77_BHB_LOOP_COUNT, cortex_a77
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#endif /* WORKAROUND_CVE_2022_23960 */
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1508412.
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* This applies only to revision <= r1p0 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1508412_wa
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/*
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* Compare x0 against revision r1p0
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*/
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mov x17, x30
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bl check_errata_1508412
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cbz x0, 3f
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/*
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* Compare x0 against revision r0p0
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*/
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bl check_errata_1508412_0
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workaround_reset_start cortex_a77, ERRATUM(1508412), ERRATA_A77_1508412
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/* move cpu revision in again and compare against r0p0 */
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mov x0, x7
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mov x1, #CPU_REV(0, 0)
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bl cpu_rev_var_ls
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cbz x0, 1f
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ldr x0, =0x0
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msr CORTEX_A77_CPUPSELR_EL3, x0
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ldr x0, =0x00E8400000
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@ -75,121 +62,38 @@ func errata_a77_1508412_wa
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2:
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ldr x0, =0x04004003FF
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msr CORTEX_A77_CPUPCR_EL3, x0
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isb
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3:
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ret x17
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endfunc errata_a77_1508412_wa
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workaround_reset_end cortex_a77, ERRATUM(1508412)
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func check_errata_1508412
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mov x1, #0x10
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b cpu_rev_var_ls
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endfunc check_errata_1508412
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func check_errata_1508412_0
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mov x1, #0x0
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b cpu_rev_var_ls
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endfunc check_errata_1508412_0
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1791578.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1791578_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_1791578
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1508412), CPU_REV(1, 0)
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workaround_reset_start cortex_a77, ERRATUM(1791578), ERRATA_A77_1791578
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/* Set bit 2 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_2
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1791578_wa
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workaround_reset_end cortex_a77, ERRATUM(1791578)
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func check_errata_1791578
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1791578
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1800714.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1800714_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1800714
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1791578), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1800714), ERRATA_A77_1800714
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/* Disable allocation of splintered pages in the L2 TLB */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1800714_wa
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workaround_reset_end cortex_a77, ERRATUM(1800714)
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func check_errata_1800714
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1800714
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1925769.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1925769_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1925769
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1800714), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1925769), ERRATA_A77_1925769
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/* Set bit 8 in ECTLR_EL1 */
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mrs x1, CORTEX_A77_CPUECTLR_EL1
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orr x1, x1, #CORTEX_A77_CPUECTLR_EL1_BIT_8
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msr CORTEX_A77_CPUECTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_1925769_wa
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workaround_reset_end cortex_a77, ERRATUM(1925769)
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func check_errata_1925769
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1925769
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #1946167.
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* This applies to revision <= r1p1 of Cortex A77.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_1946167_wa
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/* Compare x0 against revision <= r1p1 */
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mov x17, x30
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bl check_errata_1946167
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1925769), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(1946167), ERRATA_A77_1946167
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ldr x0,=0x4
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msr CORTEX_A77_CPUPSELR_EL3,x0
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ldr x0,=0x10E3900002
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@ -216,131 +120,45 @@ func errata_a77_1946167_wa
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msr CORTEX_A77_CPUPMR_EL3,x0
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ldr x0,=0x2001003FF
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msr CORTEX_A77_CPUPCR_EL3,x0
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workaround_reset_end cortex_a77, ERRATUM(1946167)
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isb
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1:
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ret x17
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endfunc errata_a77_1946167_wa
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func check_errata_1946167
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/* Applies to everything <= r1p1 */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_1946167
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/* --------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #2356587.
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a77_2356587_wa
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/* Check workaround compatibility. */
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mov x17, x30
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bl check_errata_2356587
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(1946167), CPU_REV(1, 1)
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workaround_reset_start cortex_a77, ERRATUM(2356587), ERRATA_A77_2356587
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/* Set bit 0 in ACTLR2_EL1 */
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mrs x1, CORTEX_A77_ACTLR2_EL1
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orr x1, x1, #CORTEX_A77_ACTLR2_EL1_BIT_0
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msr CORTEX_A77_ACTLR2_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a77_2356587_wa
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workaround_reset_end cortex_a77, ERRATUM(2356587)
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func check_errata_2356587
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2356587
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/* -----------------------------------------------------------------
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* Errata Workaround for Cortex A77 Errata #2743100
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* This applies to revisions r0p0, r1p0, and r1p1 and is still open.
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* -----------------------------------------------------------------
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*/
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func errata_a77_2743100_wa
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mov x17, x30
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bl check_errata_2743100
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cbz x0, 1f
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check_erratum_ls cortex_a77, ERRATUM(2356587), CPU_REV(1, 1)
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workaround_runtime_start cortex_a77, ERRATUM(2743100), ERRATA_A77_2743100
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/* dsb before isb of power down sequence */
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dsb sy
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1:
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ret x17
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endfunc errata_a77_2743100_wa
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workaround_runtime_end cortex_a77, ERRATUM(2743100), NO_ISB
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func check_errata_2743100
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/* Applies to r0p0, r1p0, and r1p1 right now */
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mov x1, #0x11
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b cpu_rev_var_ls
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endfunc check_errata_2743100
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check_erratum_ls cortex_a77, ERRATUM(2743100), CPU_REV(1, 1)
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func check_errata_cve_2022_23960
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#if WORKAROUND_CVE_2022_23960
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mov x0, #ERRATA_APPLIES
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#else
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mov x0, #ERRATA_MISSING
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#endif
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ret
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endfunc check_errata_cve_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77.
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* Shall clobber: x0-x19
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* -------------------------------------------------
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*/
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func cortex_a77_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A77_1508412
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mov x0, x18
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bl errata_a77_1508412_wa
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#endif
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#if ERRATA_A77_1925769
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mov x0, x18
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bl errata_a77_1925769_wa
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#endif
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#if ERRATA_A77_1946167
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mov x0, x18
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bl errata_a77_1946167_wa
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#endif
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#if ERRATA_A77_1791578
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mov x0, x18
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bl errata_a77_1791578_wa
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#endif
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#if ERRATA_A77_2356587
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mov x0, x18
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bl errata_a77_2356587_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2022_23960
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workaround_reset_start cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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#if IMAGE_BL31
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/*
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* The Cortex-A77 generic vectors are overridden to apply errata
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* mitigation on exception entry from lower ELs.
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*/
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adr x0, wa_cve_vbar_cortex_a77
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msr vbar_el3, x0
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#endif /* IMAGE_BL31 && WORKAROUND_CVE_2022_23960 */
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#endif /* IMAGE_BL31 */
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workaround_reset_end cortex_a77, CVE(2022, 23960)
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#if ERRATA_A77_1800714
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mov x0, x18
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bl errata_a77_1800714_wa
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#endif
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check_erratum_chosen cortex_a77, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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isb
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ret x19
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endfunc cortex_a77_reset_func
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A77. Must follow AAPCS.
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* -------------------------------------------------
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*/
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cpu_reset_func_start cortex_a77
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cpu_reset_func_end cortex_a77
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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@ -357,42 +175,14 @@ func cortex_a77_core_pwr_dwn
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#if ERRATA_A77_2743100
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mov x15, x30
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bl cpu_get_rev_var
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bl errata_a77_2743100_wa
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bl erratum_cortex_a77_2743100_wa
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mov x30, x15
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#endif /* ERRATA_A77_2743100 */
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isb
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ret
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endfunc cortex_a77_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A77. Must follow AAPCS.
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*/
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func cortex_a77_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A77_1508412, cortex_a77, 1508412
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report_errata ERRATA_A77_1791578, cortex_a77, 1791578
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report_errata ERRATA_A77_1800714, cortex_a77, 1800714
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report_errata ERRATA_A77_1925769, cortex_a77, 1925769
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report_errata ERRATA_A77_1946167, cortex_a77, 1946167
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report_errata ERRATA_A77_2356587, cortex_a77, 2356587
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report_errata ERRATA_A77_2743100, cortex_a77, 2743100
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report_errata WORKAROUND_CVE_2022_23960, cortex_a77, cve_2022_23960
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ldp x8, x30, [sp], #16
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ret
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endfunc cortex_a77_errata_report
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#endif
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errata_report_shim cortex_a77
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/* ---------------------------------------------
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* This function provides Cortex-A77 specific
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* register information for crash reporting.
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Loading…
Add table
Reference in a new issue