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plat/marvell/a8k: add Globalscale Mochabin support
Add support for Globalscale MOCHAbin board. Its based on Armada 7040 SoC and ships in multiple DRAM options: * 2GB DDR4 (1CS) * 4GB DDR4 (1CS) * 8GB DDR4 (2CS) Since it ships in multiple DRAM configurations, an Armada 3k style DDR_TOPOLOGY variable is added. Currently, this only has effect on the MOCHAbin, but I expect more boards with multiple DRAM sizes to be supported. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Change-Id: I8a1ec9268fed34f6a81c5cbf1e891f638d461305
This commit is contained in:
Robert Marko
parent
fcfecdaf2e
commit
0a6e2147e7
7 changed files with 509 additions and 0 deletions
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@ -58,6 +58,7 @@ There are several build options:
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- a3700 - A3720 DB, EspressoBin and Turris MOX
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- a70x0
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- a70x0_amc - AMC board
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- a70x0_mochabin - Globalscale MOCHAbin
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- a80x0
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- a80x0_mcbin - MacchiatoBin
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- a80x0_puzzle - IEI Puzzle-M801
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@ -150,6 +151,16 @@ A7K/8K/CN913x specific build options:
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Specify path to the MSS fimware image binary which will run on Cortex-M3 coprocessor.
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It is available in Marvell binaries-marvell git repository. Required when ``MSS_SUPPORT=1``.
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Globalscale MOCHAbin specific build options:
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- DDR_TOPOLOGY
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The DDR topology map index/name, default is 0.
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Supported Options:
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- 0 - DDR4 1CS 2GB
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- 1 - DDR4 1CS 4GB
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- 2 - DDR4 2CS 8GB
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Armada37x0 specific build options:
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227
plat/marvell/armada/a8k/a70x0_mochabin/board/dram_port.c
Normal file
227
plat/marvell/armada/a8k/a70x0_mochabin/board/dram_port.c
Normal file
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@ -0,0 +1,227 @@
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/*
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* Copyright (C) 2021 Sartura Ltd.
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* Copyright (C) 2021 Globalscale technologies, Inc.
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <arch_helpers.h>
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#include <common/debug.h>
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#include <mv_ddr_if.h>
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#include <plat_marvell.h>
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/*
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* This function may modify the default DRAM parameters
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* based on information received from SPD or bootloader
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* configuration located on non volatile storage
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*/
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void plat_marvell_dram_update_topology(void)
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{
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}
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/*
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* This struct provides the DRAM training code with
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* the appropriate board DRAM configuration
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*/
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#if DDR_TOPOLOGY == 0
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static struct mv_ddr_topology_map board_topology_map_2g = {
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/* 1CS 4Gb x4 devices of Samsung K4A4G085WF */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_4GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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#if DDR_TOPOLOGY == 1
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static struct mv_ddr_topology_map board_topology_map_4g = {
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/* 1CS 8Gb x4 devices of Samsung K4A8G085WC-BCTD */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0},
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{0x1, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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#if DDR_TOPOLOGY == 2
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static struct mv_ddr_topology_map board_topology_map_8g = {
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/* 2CS 8Gb x8 devices of Micron MT40A1G8WE-083E IT */
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DEBUG_LEVEL_ERROR,
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0x1, /* active interfaces */
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/* cs_mask, mirror, dqs_swap, ck_swap X subphys */
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{ { { {0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0},
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{0x3, 0x2, 0, 0} },
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SPEED_BIN_DDR_2400R, /* speed_bin */
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MV_DDR_DEV_WIDTH_8BIT, /* sdram device width */
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MV_DDR_DIE_CAP_8GBIT, /* die capacity */
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MV_DDR_FREQ_SAR, /* frequency */
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0, 0, /* cas_l, cas_wl */
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MV_DDR_TEMP_LOW} }, /* temperature */
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BUS_MASK_32BIT, /* subphys mask */
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MV_DDR_CFG_DEFAULT, /* ddr configuration data source */
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NOT_COMBINED, /* ddr twin-die combined*/
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{ {0} }, /* raw spd data */
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{0}, /* timing parameters */
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{ /* electrical configuration */
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{ /* memory electrical configuration */
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MV_DDR_RTT_NOM_PARK_RZQ_DISABLE, /* rtt_nom */
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{
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MV_DDR_RTT_NOM_PARK_RZQ_DIV4, /* rtt_park 1cs */
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MV_DDR_RTT_NOM_PARK_RZQ_DIV1 /* rtt_park 2cs */
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},
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{
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MV_DDR_RTT_WR_DYN_ODT_OFF, /* rtt_wr 1cs */
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MV_DDR_RTT_WR_RZQ_DIV2 /* rtt_wr 2cs */
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},
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MV_DDR_DIC_RZQ_DIV7 /* dic */
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},
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{ /* phy electrical configuration */
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MV_DDR_OHM_30, /* data_drv_p */
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MV_DDR_OHM_30, /* data_drv_n */
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MV_DDR_OHM_30, /* ctrl_drv_p */
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MV_DDR_OHM_30, /* ctrl_drv_n */
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{
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MV_DDR_OHM_60, /* odt_p 1cs */
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MV_DDR_OHM_120 /* odt_p 2cs */
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},
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{
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MV_DDR_OHM_60, /* odt_n 1cs */
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MV_DDR_OHM_120 /* odt_n 2cs */
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},
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},
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{ /* mac electrical configuration */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_pattern */
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MV_DDR_ODT_CFG_ALWAYS_ON, /* odtcfg_write */
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MV_DDR_ODT_CFG_NORMAL, /* odtcfg_read */
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},
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}
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};
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#endif
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struct mv_ddr_topology_map *mv_ddr_topology_map_get(void)
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{
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/* a70x0_mochabin board supports 3 DDR4 models (2G/1CS, 4G/1CS, 8G/2CS) */
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#if DDR_TOPOLOGY == 0
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return &board_topology_map_2g;
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#elif DDR_TOPOLOGY == 1
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return &board_topology_map_4g;
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#elif DDR_TOPOLOGY == 2
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return &board_topology_map_8g;
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#else
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#error "Unknown DDR topology"
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#endif
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}
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@ -0,0 +1,145 @@
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/*
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* Copyright (C) 2021 Sartura Ltd.
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* Copyright (C) 2021 Globalscale technologies, Inc.
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#include <armada_common.h>
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/*
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* If bootrom is currently at BLE there's no need to include the memory
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* maps structure at this point
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*/
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#include <mvebu_def.h>
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* AMB Configuration
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*****************************************************************************
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*/
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struct addr_map_win amb_memory_map[] = {
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/* CP0 SPI1 CS0 Direct Mode access */
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{0xf900, 0x1000000, AMB_SPI1_CS0_ID},
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};
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int marvell_get_amb_memory_map(struct addr_map_win **win,
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uint32_t *size, uintptr_t base)
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{
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*win = amb_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(amb_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* IO_WIN Configuration
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*****************************************************************************
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*/
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struct addr_map_win io_win_memory_map[] = {
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#ifndef IMAGE_BLE
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/* MCI 0 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(0), 0x100000, MCI_0_TID},
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/* MCI 1 indirect window */
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{MVEBU_MCI_REG_BASE_REMAP(1), 0x100000, MCI_1_TID},
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#endif
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};
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uint32_t marvell_get_io_win_gcr_target(int ap_index)
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{
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return PIDI_TID;
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}
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int marvell_get_io_win_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = io_win_memory_map;
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if (*win == NULL)
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*size = 0;
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else
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*size = ARRAY_SIZE(io_win_memory_map);
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return 0;
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}
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#ifndef IMAGE_BLE
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/*****************************************************************************
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* IOB Configuration
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*****************************************************************************
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*/
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struct addr_map_win iob_memory_map[] = {
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/* PEX1_X1 window */
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{0x00000000f7000000, 0x1000000, PEX1_TID},
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/* PEX2_X1 window */
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{0x00000000f8000000, 0x1000000, PEX2_TID},
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{0x00000000c0000000, 0x30000000, PEX2_TID},
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{0x0000000800000000, 0x100000000, PEX2_TID},
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/* PEX0_X4 window */
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{0x00000000f6000000, 0x1000000, PEX0_TID},
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/* SPI1_CS0 (RUNIT) window */
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{0x00000000f9000000, 0x1000000, RUNIT_TID},
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};
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int marvell_get_iob_memory_map(struct addr_map_win **win, uint32_t *size,
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uintptr_t base)
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{
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*win = iob_memory_map;
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*size = ARRAY_SIZE(iob_memory_map);
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return 0;
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}
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#endif
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/*****************************************************************************
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* CCU Configuration
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*****************************************************************************
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*/
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struct addr_map_win ccu_memory_map[] = { /* IO window */
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#ifdef IMAGE_BLE
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{0x00000000f2000000, 0x4000000, IO_0_TID}, /* IO window */
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#else
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#if LLC_SRAM
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/* This entry is prepared for OP-TEE OS that enables the LLC SRAM
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* and changes the window target to SRAM_TID.
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*/
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{PLAT_MARVELL_LLC_SRAM_BASE, PLAT_MARVELL_LLC_SRAM_SIZE, DRAM_0_TID},
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#endif
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{0x00000000f2000000, 0xe000000, IO_0_TID},
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{0x00000000c0000000, 0x30000000, IO_0_TID}, /* IO window */
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{0x0000000800000000, 0x100000000, IO_0_TID}, /* IO window */
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#endif
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};
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uint32_t marvell_get_ccu_gcr_target(int ap)
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{
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return DRAM_0_TID;
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}
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int marvell_get_ccu_memory_map(int ap_index, struct addr_map_win **win,
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uint32_t *size)
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{
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*win = ccu_memory_map;
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*size = ARRAY_SIZE(ccu_memory_map);
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return 0;
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}
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#ifdef IMAGE_BLE
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/*****************************************************************************
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* SKIP IMAGE Configuration
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*****************************************************************************
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*/
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#if PLAT_RECOVERY_IMAGE_ENABLE
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void *plat_marvell_get_skip_image_data(void)
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{
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/* No recovery button on a70x0_mochabin board */
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return NULL;
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}
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#endif
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#endif
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@ -0,0 +1,87 @@
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/*
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* Copyright (C) 2021 Sartura Ltd.
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* Copyright (C) 2021 Globalscale technologies, Inc.
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* Copyright (C) 2021 Marvell International Ltd.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* https://spdx.org/licenses
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*/
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#ifndef __PHY_PORTING_LAYER_H
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#define __PHY_PORTING_LAYER_H
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#define MAX_LANE_NR 6
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static const struct xfi_params
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xfi_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
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/* AP0 */
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{
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/* CP 0 */
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{
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{ 0 }, /* Comphy0 */
|
||||
{ 0 }, /* Comphy1 */
|
||||
{ 0 }, /* Comphy2 */
|
||||
{ 0 }, /* Comphy3 */
|
||||
{ .g1_ffe_res_sel = 0x3, .g1_ffe_cap_sel = 0xf, .align90 = 0x60,
|
||||
.g1_dfe_res = 0x1, .g1_amp = 0x1c, .g1_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g1_tx_amp_adj = 0x1, .g1_tx_emph_en = 0x1,
|
||||
.g1_tx_emph = 0x0, .g1_rx_selmuff = 0x1, .g1_rx_selmufi = 0x0,
|
||||
.g1_rx_selmupf = 0x2, .g1_rx_selmupi = 0x2,
|
||||
.valid = 1 }, /* Comphy4 */
|
||||
{ 0 }, /* Comphy5 */
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct sata_params
|
||||
sata_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
|
||||
/* AP0 */
|
||||
{
|
||||
/* CP 0 */
|
||||
{
|
||||
{ 0 }, /* Comphy0 */
|
||||
{ 0 }, /* Comphy1 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy2 */
|
||||
{ .g1_amp = 0x8, .g2_amp = 0xa, .g3_amp = 0x1e,
|
||||
.g1_emph = 0x1, .g2_emph = 0x2, .g3_emph = 0xe,
|
||||
.g1_emph_en = 0x1, .g2_emph_en = 0x1, .g3_emph_en = 0x1,
|
||||
.g1_tx_amp_adj = 0x1, .g2_tx_amp_adj = 0x1, .g3_tx_amp_adj = 0x1,
|
||||
.g1_tx_emph_en = 0x0, .g2_tx_emph_en = 0x0, .g3_tx_emph_en = 0x0,
|
||||
.g1_tx_emph = 0x1, .g2_tx_emph = 0x1, .g3_tx_emph = 0x1,
|
||||
.g3_dfe_res = 0x1, .g3_ffe_res_sel = 0x4, .g3_ffe_cap_sel = 0xf,
|
||||
.align90 = 0x61,
|
||||
.g1_rx_selmuff = 0x3, .g2_rx_selmuff = 0x3, .g3_rx_selmuff = 0x3,
|
||||
.g1_rx_selmufi = 0x0, .g2_rx_selmufi = 0x0, .g3_rx_selmufi = 0x3,
|
||||
.g1_rx_selmupf = 0x1, .g2_rx_selmupf = 0x1, .g3_rx_selmupf = 0x2,
|
||||
.g1_rx_selmupi = 0x0, .g2_rx_selmupi = 0x0, .g3_rx_selmupi = 0x2,
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT,
|
||||
.valid = 0x1
|
||||
}, /* Comphy3 */
|
||||
{ 0 }, /* Comphy4 */
|
||||
{ 0 }, /* Comphy5 */
|
||||
},
|
||||
},
|
||||
};
|
||||
|
||||
static const struct usb_params
|
||||
usb_static_values_tab[AP_NUM][CP_NUM][MAX_LANE_NR] = {
|
||||
[0 ... AP_NUM-1][0 ... CP_NUM-1][0 ... MAX_LANE_NR-1] = {
|
||||
.polarity_invert = COMPHY_POLARITY_NO_INVERT
|
||||
},
|
||||
};
|
||||
|
||||
#endif /* __PHY_PORTING_LAYER_H */
|
||||
15
plat/marvell/armada/a8k/a70x0_mochabin/mvebu_def.h
Normal file
15
plat/marvell/armada/a8k/a70x0_mochabin/mvebu_def.h
Normal file
|
|
@ -0,0 +1,15 @@
|
|||
/*
|
||||
* Copyright (C) 2021 Marvell International Ltd.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
* https://spdx.org/licenses
|
||||
*/
|
||||
|
||||
#ifndef MVEBU_DEF_H
|
||||
#define MVEBU_DEF_H
|
||||
|
||||
#include <a8k_plat_def.h>
|
||||
|
||||
#define CP_COUNT 1 /* A70x0 has single CP0 */
|
||||
|
||||
#endif /* MVEBU_DEF_H */
|
||||
20
plat/marvell/armada/a8k/a70x0_mochabin/platform.mk
Normal file
20
plat/marvell/armada/a8k/a70x0_mochabin/platform.mk
Normal file
|
|
@ -0,0 +1,20 @@
|
|||
#
|
||||
# Copyright (C) 2021 Marvell International Ltd.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
# https://spdx.org/licenses
|
||||
#
|
||||
|
||||
PCI_EP_SUPPORT := 0
|
||||
|
||||
CP_NUM := 1
|
||||
$(eval $(call add_define,CP_NUM))
|
||||
|
||||
DOIMAGE_SEC := tools/doimage/secure/sec_img_7K.cfg
|
||||
|
||||
MARVELL_MOCHI_DRV := drivers/marvell/mochi/apn806_setup.c
|
||||
|
||||
BOARD_DIR := $(shell dirname $(lastword $(MAKEFILE_LIST)))
|
||||
include plat/marvell/armada/a8k/common/a8k_common.mk
|
||||
|
||||
include plat/marvell/armada/common/marvell_common.mk
|
||||
|
|
@ -75,6 +75,10 @@ endif
|
|||
# This define specifies DDR type for BLE
|
||||
$(eval $(call add_define,CONFIG_DDR4))
|
||||
|
||||
# This define specifies DDR topology for BLE
|
||||
DDR_TOPOLOGY ?= 0
|
||||
$(eval $(call add_define,DDR_TOPOLOGY))
|
||||
|
||||
MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
|
|
|
|||
Loading…
Add table
Reference in a new issue