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Merge changes from topic "ms/cpu_errata" into integration
* changes: refactor(cpus): add Cortex-A72 errata information refactor(cpus): convert Rainier to use errata framework refactor(cpus): convert QEMU Max to use the errata framework
This commit is contained in:
Lauren Wehrmeister
TrustedFirmware Code Review
commit
098312edf7
3 changed files with 25 additions and 115 deletions
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2022, Arm Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -87,11 +87,15 @@ func check_errata_859971
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b cpu_rev_var_ls
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endfunc check_errata_859971
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add_erratum_entry cortex_a72, ERRATUM(859971), ERRATA_A72_859971
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func check_errata_cve_2017_5715
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mov r0, #ERRATA_MISSING
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bx lr
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endfunc check_errata_cve_2017_5715
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add_erratum_entry cortex_a72, CVE(2017, 5715), WORKAROUND_CVE_2017_5715
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func check_errata_cve_2018_3639
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#if WORKAROUND_CVE_2018_3639
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mov r0, #ERRATA_APPLIES
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@ -101,11 +105,15 @@ func check_errata_cve_2018_3639
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bx lr
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endfunc check_errata_cve_2018_3639
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add_erratum_entry cortex_a72, CVE(2018, 3639), WORKAROUND_CVE_2018_3639
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func check_errata_cve_2022_23960
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mov r0, #ERRATA_MISSING
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bx lr
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endfunc check_errata_cve_2022_23960
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add_erratum_entry cortex_a72, CVE(2022, 23960), WORKAROUND_CVE_2022_23960
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A72.
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* -------------------------------------------------
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@ -248,29 +256,7 @@ func cortex_a72_cluster_pwr_dwn
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b cortex_a72_disable_ext_debug
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endfunc cortex_a72_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A72. Must follow AAPCS.
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*/
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func cortex_a72_errata_report
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push {r12, lr}
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bl cpu_get_rev_var
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mov r4, r0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_A72_859971, cortex_a72, 859971
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report_errata WORKAROUND_CVE_2017_5715, cortex_a72, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a72, cve_2018_3639
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report_errata WORKAROUND_CVE_2022_23960, cortex_a72, cve_2022_23960
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pop {r12, lr}
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bx lr
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endfunc cortex_a72_errata_report
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#endif
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errata_report_shim cortex_a72
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declare_cpu_ops cortex_a72, CORTEX_A72_MIDR, \
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cortex_a72_reset_func, \
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2014-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2014-2023, Arm Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -47,14 +47,7 @@ func qemu_max_cluster_pwr_dwn
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b dcsw_op_all
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endfunc qemu_max_cluster_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for QEMU "max". Must follow AAPCS.
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*/
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func qemu_max_errata_report
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ret
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endfunc qemu_max_errata_report
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#endif
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errata_report_shim qemu_max
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/* ---------------------------------------------
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* This function provides cpu specific
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2020-2022, Arm Limited. All rights reserved.
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* Copyright (c) 2020-2023, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -41,78 +41,30 @@ func rainier_disable_speculative_loads
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ret
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endfunc rainier_disable_speculative_loads
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/* --------------------------------------------------
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* Errata Workaround for Neoverse N1 Errata #1868343.
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* This applies to revision <= r4p0 of Neoverse N1.
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* This workaround is the same as the workaround for
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* errata 1262606 and 1275112 but applies to a wider
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* revision range.
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* Rainier R0P0 is based on Neoverse N1 R4P0 so the
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* workaround checks for r0p0 version of Rainier CPU.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0, x1 & x17
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* --------------------------------------------------
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*/
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func errata_n1_1868343_wa
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/*
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* Compare x0 against revision r4p0
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*/
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mov x17, x30
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bl check_errata_1868343
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cbz x0, 1f
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mrs x1, RAINIER_CPUACTLR_EL1
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orr x1, x1, RAINIER_CPUACTLR_EL1_BIT_13
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msr RAINIER_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_n1_1868343_wa
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/* Rainier R0P0 is based on Neoverse N1 R4P0. */
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workaround_reset_start rainier, ERRATUM(1868343), ERRATA_N1_1868343
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sysreg_bit_set RAINIER_CPUACTLR_EL1, RAINIER_CPUACTLR_EL1_BIT_13
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workaround_reset_end rainier, ERRATUM(1868343)
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func check_errata_1868343
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/* Applies to r0p0 of Rainier CPU */
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_1868343
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func rainier_reset_func
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mov x19, x30
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check_erratum_ls rainier, ERRATUM(1868343), CPU_REV(0, 0)
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cpu_reset_func_start rainier
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bl rainier_disable_speculative_loads
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/* Forces all cacheable atomic instructions to be near */
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mrs x0, RAINIER_CPUACTLR2_EL1
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orr x0, x0, #RAINIER_CPUACTLR2_EL1_BIT_2
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msr RAINIER_CPUACTLR2_EL1, x0
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isb
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_N1_1868343
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mov x0, x18
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bl errata_n1_1868343_wa
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#endif
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sysreg_bit_set RAINIER_CPUACTLR2_EL1, RAINIER_CPUACTLR2_EL1_BIT_2
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#if ENABLE_FEAT_AMU
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/* Make sure accesses from EL0/EL1 and EL2 are not trapped to EL3 */
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mrs x0, actlr_el3
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orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
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msr actlr_el3, x0
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sysreg_bit_set actlr_el3, RAINIER_ACTLR_AMEN_BIT
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/* Make sure accesses from EL0/EL1 are not trapped to EL2 */
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mrs x0, actlr_el2
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orr x0, x0, #RAINIER_ACTLR_AMEN_BIT
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msr actlr_el2, x0
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sysreg_bit_set actlr_el2, RAINIER_ACTLR_AMEN_BIT
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/* Enable group0 counters */
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mov x0, #RAINIER_AMU_GROUP0_MASK
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msr CPUAMCNTENSET_EL0, x0
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#endif
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isb
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ret x19
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endfunc rainier_reset_func
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cpu_reset_func_end rainier
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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@ -123,33 +75,12 @@ func rainier_core_pwr_dwn
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, RAINIER_CPUPWRCTLR_EL1
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orr x0, x0, #RAINIER_CORE_PWRDN_EN_MASK
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msr RAINIER_CPUPWRCTLR_EL1, x0
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sysreg_bit_set RAINIER_CPUPWRCTLR_EL1, RAINIER_CORE_PWRDN_EN_MASK
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isb
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ret
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endfunc rainier_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Rainier. Must follow AAPCS.
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*/
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func rainier_errata_report
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stp x8, x30, [sp, #-16]!
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bl cpu_get_rev_var
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mov x8, x0
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/*
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* Report all errata. The revision-variant information is passed to
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* checking functions of each errata.
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*/
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report_errata ERRATA_N1_1868343, rainier, 1868343
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ldp x8, x30, [sp], #16
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ret
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endfunc rainier_errata_report
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#endif
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errata_report_shim rainier
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/* ---------------------------------------------
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* This function provides Rainier specific
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