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doc: Correct CPACR.FPEN usage

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To avoid trapping from EL0/1, FPEN bits need to be set 0x3, not
clearing.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Change-Id: Ic34e9aeb876872883c5f040618ed6d50f21dacd0
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Peng Fan 2020-08-21 10:47:17 +08:00 • committed by Peng Fan
parent 34029d01c6
commit 093ba62e14
1 changed files with 1 additions and 1 deletions
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docs/design/firmware-design.rst
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@ -369,7 +369,7 @@ Architectural initialization
For AArch64, BL2 performs the minimal architectural initialization required For AArch64, BL2 performs the minimal architectural initialization required
for subsequent stages of TF-A and normal world software. EL1 and EL0 are given for subsequent stages of TF-A and normal world software. EL1 and EL0 are given
access to Floating Point and Advanced SIMD registers by clearing the access to Floating Point and Advanced SIMD registers by setting the
``CPACR.FPEN`` bits. ``CPACR.FPEN`` bits.
For AArch32, the minimal architectural initialization required for subsequent For AArch32, the minimal architectural initialization required for subsequent