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Merge "feat(intel): restructure watchdog" into integration

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This commit is contained in:
Manish Pandey 2023-11-28 22:45:38 +01:00 • committed by TrustedFirmware Code Review
commit 091f42a674
5 changed files with 22 additions and 5 deletions
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5
plat/intel/soc/agilex/include/socfpga_plat_def.h
View file

@ -76,6 +76,11 @@
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define WDT_BASE (0xFFD00200)
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/

5
plat/intel/soc/agilex5/include/socfpga_plat_def.h
View file

@ -97,6 +97,11 @@
#define PLAT_UART0_BASE (0x10C02000) #define PLAT_UART0_BASE (0x10C02000)
#define PLAT_UART1_BASE (0x10C02100) #define PLAT_UART1_BASE (0x10C02100)
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define WDT_BASE (0x10D00200)
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/

7
plat/intel/soc/common/drivers/wdt/watchdog.h
View file

@ -7,11 +7,8 @@
#ifndef CAD_WATCHDOG_H #ifndef CAD_WATCHDOG_H
#define CAD_WATCHDOG_H #define CAD_WATCHDOG_H
#if PLATFORM_MODEL == PLAT_SOCFPGA_AGILEX5 #include "socfpga_plat_def.h"
#define WDT_BASE (0x10D00200)
#else
#define WDT_BASE (0xFFD00200)
#endif
#define WDT_REG_SIZE_OFFSET (0x4) #define WDT_REG_SIZE_OFFSET (0x4)
#define WDT_MIN_CYCLES (65536) #define WDT_MIN_CYCLES (65536)
#define WDT_PERIOD (20) #define WDT_PERIOD (20)

5
plat/intel/soc/n5x/include/socfpga_plat_def.h
View file

@ -77,6 +77,11 @@
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define WDT_BASE (0xFFD00200)
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/

5
plat/intel/soc/stratix10/include/socfpga_plat_def.h
View file

@ -75,6 +75,11 @@
#define PLAT_UART0_BASE (0xFFC02000) #define PLAT_UART0_BASE (0xFFC02000)
#define PLAT_UART1_BASE (0xFFC02100) #define PLAT_UART1_BASE (0xFFC02100)
/*******************************************************************************
* WDT related constants
******************************************************************************/
#define WDT_BASE (0xFFD00200)
/******************************************************************************* /*******************************************************************************
* GIC related constants * GIC related constants
******************************************************************************/ ******************************************************************************/