diff --git a/docs/plat/arm/fvp/index.rst b/docs/plat/arm/fvp/index.rst
index b28c24758..42c0eda25 100644
--- a/docs/plat/arm/fvp/index.rst
+++ b/docs/plat/arm/fvp/index.rst
@@ -12,61 +12,59 @@ Arm FVPs without shifted affinities, and that do not support threaded CPU cores
 (64-bit host machine only).
 
 .. note::
-   The FVP models used are Version 11.17 Build 21, unless otherwise stated.
+   The FVP models used are Version 11.19 Build 14, unless otherwise stated.
 
 -  ``Foundation_Platform``
--  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502``
--  ``FVP_Base_AEMv8A-AEMv8A`` (For certain configurations also uses 11.14/21)
--  ``FVP_Base_AEMv8A-GIC600AE``
--  ``FVP_Base_AEMvA``         (For certain configurations also uses 0.0/6684)
--  ``FVP_Base_Cortex-A32x4``  (Version 11.12/38)
+-  ``FVP_Base_AEMv8A-AEMv8A-AEMv8A-AEMv8A-CCN502`` (Version 11.17/21)
+-  ``FVP_Base_AEMv8A-GIC600AE`` (Version 11.17/21)
+-  ``FVP_Base_AEMvA``
+-  ``FVP_Base_AEMvA-AEMvA``
+-  ``FVP_Base_Cortex-A32x4`` (Version 11.12/38)
 -  ``FVP_Base_Cortex-A35x4``
 -  ``FVP_Base_Cortex-A53x4``
--  ``FVP_Base_Cortex-A55x4``
+-  ``FVP_Base_Cortex-A55``
 -  ``FVP_Base_Cortex-A55x4+Cortex-A75x4``
+-  ``FVP_Base_Cortex-A55x4+Cortex-A76x2``
 -  ``FVP_Base_Cortex-A57x1-A53x1``
 -  ``FVP_Base_Cortex-A57x2-A53x4``
--  ``FVP_Base_Cortex-A57x4-A53x4``
 -  ``FVP_Base_Cortex-A57x4``
--  ``FVP_Base_Cortex-A65AEx8``
--  ``FVP_Base_Cortex-A65x4``
--  ``FVP_Base_Cortex-A710x4``
--  ``FVP_Base_Cortex-A72x4-A53x4``
+-  ``FVP_Base_Cortex-A57x4-A53x4``
+-  ``FVP_Base_Cortex-A65``
+-  ``FVP_Base_Cortex-A65AE``
+-  ``FVP_Base_Cortex-A710x4`` (Version 11.17/21)
 -  ``FVP_Base_Cortex-A72x4``
--  ``FVP_Base_Cortex-A73x4-A53x4``
+-  ``FVP_Base_Cortex-A72x4-A53x4``
 -  ``FVP_Base_Cortex-A73x4``
--  ``FVP_Base_Cortex-A75x4``
--  ``FVP_Base_Cortex-A76AEx4``
--  ``FVP_Base_Cortex-A76AEx8``
--  ``FVP_Base_Cortex-A76x4``
--  ``FVP_Base_Cortex-A77x4``
--  ``FVP_Base_Cortex-A78x4``
--  ``FVP_Base_Neoverse-E1x1``
--  ``FVP_Base_Neoverse-E1x2``
--  ``FVP_Base_Neoverse-E1x4``
--  ``FVP_Base_Neoverse-N1x4``
--  ``FVP_Base_Neoverse-N2x4`` (Version 11.12 build 38)
--  ``FVP_Base_Neoverse-V1x4``
--  ``FVP_Base_RevC-2xAEMvA``  (For certain configurations also uses 0.0/6557)
--  ``FVP_CSS_SGI-575``        (Version 11.17/33)
+-  ``FVP_Base_Cortex-A73x4-A53x4``
+-  ``FVP_Base_Cortex-A75``
+-  ``FVP_Base_Cortex-A76``
+-  ``FVP_Base_Cortex-A76AE``
+-  ``FVP_Base_Cortex-A77``
+-  ``FVP_Base_Cortex-A78``
+-  ``FVP_Base_Cortex-A78C``
+-  ``FVP_Base_Cortex-X2x4`` (Version 11.17/21)
+-  ``FVP_Base_Neoverse-E1``
+-  ``FVP_Base_Neoverse-N1``
+-  ``FVP_Base_Neoverse-N2x4`` (Version 11.16/16)
+-  ``FVP_Base_Neoverse-V1``
+-  ``FVP_Base_RevC-2xAEMvA``
 -  ``FVP_Morello``            (Version 0.11/33)
--  ``FVP_RD_E1_edge``         (Version 11.17/33)
--  ``FVP_RD_N1_edge_dual``    (Version 11.17/33)
--  ``FVP_RD_N1_edge``         (Version 11.17/33)
--  ``FVP_RD_V1``              (Version 11.17/33)
--  ``FVP_TC0``
--  ``FVP_TC1``
+-  ``FVP_RD_E1_edge``         (Version 11.17/29)
+-  ``FVP_RD_V1``              (Version 11.17/29)
+-  ``FVP_TC0`` (Version 11.17/18)
+-  ``FVP_TC1`` (Version 11.17/33)
+-  ``FVP_TC2`` (Version 11.18/28)
 
 The latest version of the AArch32 build of TF-A has been tested on the
 following Arm FVPs without shifted affinities, and that do not support threaded
 CPU cores (64-bit host machine only).
 
 -  ``FVP_Base_AEMvA``
--  ``FVP_Base_AEMv8A-AEMv8A``
+-  ``FVP_Base_AEMvA-AEMvA``
 -  ``FVP_Base_Cortex-A32x4``
 
 .. note::
-   The ``FVP_Base_RevC-2xAEMv8A`` FVP only supports shifted affinities, which
+   The ``FVP_Base_RevC-2xAEMvA`` FVP only supports shifted affinities, which
    is not compatible with legacy GIC configurations. Therefore this FVP does not
    support these legacy GIC configurations.