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Merge "fix(plat/marvell/a3720/uart): fix UART parent clock rate determination" into integration

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This commit is contained in:
Manish Pandey 2021-06-07 15:36:46 +02:00 • committed by TrustedFirmware Code Review
commit 076bb38df5
7 changed files with 49 additions and 25 deletions
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24
drivers/marvell/comphy/phy-comphy-3700.c
View file

@ -14,6 +14,7 @@
#include <mvebu.h>
#include <mvebu_def.h>
#include <plat_marvell.h>
#include "phy-comphy-3700.h"
#include "phy-comphy-common.h"
@ -29,15 +30,6 @@
#define USB3_GBE1_PHY (MVEBU_REGS_BASE + 0x5C000)
#define COMPHY_SD_ADDR (MVEBU_REGS_BASE + 0x1F000)
/*
* Below address in used only for reading, therefore no problem with concurrent
* Linux access.
*/
#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
#define MVEBU_XTAL_MODE_MASK BIT(9)
#define MVEBU_XTAL_MODE_OFFS 9
#define MVEBU_XTAL_CLOCK_25MHZ 0x0
struct sgmii_phy_init_data_fix {
uint16_t addr;
uint16_t value;
@ -125,20 +117,6 @@ static uint16_t sgmii_phy_init[512] = {
0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000, 0x0000 /*1F8 */
};
/* returns reference clock in MHz (25 or 40) */
static uint32_t get_ref_clk(void)
{
uint32_t val;
val = (mmio_read_32(MVEBU_TEST_PIN_LATCH_N) & MVEBU_XTAL_MODE_MASK) >>
MVEBU_XTAL_MODE_OFFS;
if (val == MVEBU_XTAL_CLOCK_25MHZ)
return 25;
else
return 40;
}
/* PHY selector configures with corresponding modes */
static void mvebu_a3700_comphy_set_phy_selector(uint8_t comphy_index,
uint32_t comphy_mode)

2
include/plat/marvell/armada/a3k/common/plat_marvell.h
View file

@ -100,4 +100,6 @@ void plat_marvell_interconnect_enter_coherency(void);
const mmap_region_t *plat_marvell_get_mmap(void);
uint32_t get_ref_clk(void);
#endif /* PLAT_MARVELL_H */

1
plat/marvell/armada/a3k/common/a3700_common.mk
View file

@ -38,6 +38,7 @@ PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
$(PLAT_COMMON_BASE)/aarch64/a3700_clock.S \
$(MARVELL_DRV_BASE)/uart/a3700_console.S
BL1_SOURCES += $(PLAT_COMMON_BASE)/aarch64/plat_helpers.S \

35
plat/marvell/armada/a3k/common/aarch64/a3700_clock.S Normal file
View file

@ -0,0 +1,35 @@
/*
* Copyright (C) 2018 Marvell International Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
* https://spdx.org/licenses
*/
#include <asm_macros.S>
#include <platform_def.h>
/*
* Below address in used only for reading, therefore no problem with concurrent
* Linux access.
*/
#define MVEBU_TEST_PIN_LATCH_N (MVEBU_NB_GPIO_REG_BASE + 0x8)
#define MVEBU_XTAL_MODE_MASK BIT(9)
/* -----------------------------------------------------
* uint32_t get_ref_clk (void);
*
* returns reference clock in MHz (25 or 40)
* -----------------------------------------------------
*/
.globl get_ref_clk
func get_ref_clk
mov_imm x0, MVEBU_TEST_PIN_LATCH_N
ldr w0, [x0]
tst w0, #MVEBU_XTAL_MODE_MASK
bne 40
mov w0, #25
ret
40:
mov w0, #40
ret
endfunc get_ref_clk

1
plat/marvell/armada/a3k/common/include/platform_def.h
View file

@ -164,7 +164,6 @@
* PL011 related constants
*/
#define PLAT_MARVELL_UART_BASE (MVEBU_REGS_BASE + 0x12000)
#define PLAT_MARVELL_UART_CLK_IN_HZ 25000000
/* Required platform porting definitions */
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1

10
plat/marvell/armada/common/aarch64/marvell_helpers.S
View file

@ -63,8 +63,16 @@ endfunc plat_marvell_calc_core_pos
* ---------------------------------------------
*/
func plat_crash_console_init
mov_imm x0, PLAT_MARVELL_UART_BASE
#ifdef PLAT_a3700
mov x1, x30
bl get_ref_clk
mov x30, x1
mov_imm x1, 1000000
mul x1, x0, x1
#else
mov_imm x1, PLAT_MARVELL_UART_CLK_IN_HZ
#endif
mov_imm x0, PLAT_MARVELL_UART_BASE
mov_imm x2, MARVELL_CONSOLE_BAUDRATE
#ifdef PLAT_a3700
b console_a3700_core_init

1
plat/marvell/armada/common/marvell_console.c
View file

@ -14,6 +14,7 @@
#ifdef PLAT_a3700
#include <drivers/marvell/uart/a3700_console.h>
#define PLAT_MARVELL_UART_CLK_IN_HZ (get_ref_clk() * 1000000)
#define console_marvell_register console_a3700_register
#else
#include <drivers/ti/uart/uart_16550.h>