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refactor(st-ddr): add definition for timeouts and delays

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Instead of using hard-coded number in DDR driver, use macros.
Modify TIMEOUT_US_1S to DDR_TIMEOUT_US_1S to align with other defines.

Signed-off-by: Yann Gautier <yann.gautier@st.com>
Change-Id: I489084132821774b0049a4a5d7fc30db24a7bb11
This commit is contained in:
Yann Gautier 2024-05-29 15:34:45 +02:00 • committed by Maxime Méré
parent 87cd847ce5
commit 066a5958e7
3 changed files with 13 additions and 8 deletions
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10
drivers/st/ddr/stm32mp1_ddr.c
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@ -1,5 +1,5 @@
/*
* Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved
* Copyright (C) 2018-2024, STMicroelectronics - All Rights Reserved
*
* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
*/
@ -215,7 +215,7 @@ static void stm32mp1_ddrphy_idone_wait(struct stm32mp_ddrphy *phy)
{
uint32_t pgsr;
int error = 0;
uint64_t timeout = timeout_init_us(TIMEOUT_US_1S);
uint64_t timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
do {
pgsr = mmio_read_32((uintptr_t)&phy->pgsr);
@ -266,7 +266,7 @@ static void stm32mp1_ddrphy_init(struct stm32mp_ddrphy *phy, uint32_t pir)
mmio_read_32((uintptr_t)&phy->pir));
/* Need to wait 10 configuration clock before start polling */
udelay(10);
udelay(DDR_DELAY_10US);
/* Wait DRAM initialization and Gate Training Evaluation complete */
stm32mp1_ddrphy_idone_wait(phy);
@ -279,7 +279,7 @@ static void stm32mp1_wait_operating_mode(struct stm32mp_ddr_priv *priv, uint32_t
uint32_t stat;
int break_loop = 0;
timeout = timeout_init_us(TIMEOUT_US_1S);
timeout = timeout_init_us(DDR_TIMEOUT_US_1S);
for ( ; ; ) {
uint32_t operating_mode;
uint32_t selref_type;
@ -614,7 +614,7 @@ void stm32mp1_ddr_init(struct stm32mp_ddr_priv *priv,
mmio_clrbits_32(priv->rcc + RCC_DDRITFCR, RCC_DDRITFCR_DDRCAPBRST);
/* 1.4. wait 128 cycles to permit initialization of end logic */
udelay(2);
udelay(DDR_DELAY_2US);
/* For PCLK = 133MHz => 1 us is enough, 2 to allow lower frequency */
/* 1.5. initialize registers ddr_umctl2 */