From 050c4a38a335c721c2f6ce38c33f1aa6aa328800 Mon Sep 17 00:00:00 2001 From: Govindraj Raja Date: Tue, 21 Jan 2025 17:12:33 -0600 Subject: [PATCH] fix(cpus): workaround for Cortex-A720 erratum 3699561 Cortex-A720 erratum 3699561 that applies to all revisions <= r0p2 and is still Open. The workaround is for EL3 software that performs context save/restore on a change of Security state to use a value of SCR_EL3.NS when accessing ICH_VMCR_EL2 that reflects the Security state that owns the data being saved or restored. SDEN documentation: https://developer.arm.com/documentation/SDEN-2439421/latest/ Change-Id: I7ea3aaf3e7bf6b4f3648f6872e505a41247b14ba Signed-off-by: Govindraj Raja --- docs/design/cpu-specific-build-macros.rst | 4 ++++ include/lib/cpus/aarch64/cortex_a720.h | 6 +++++- lib/cpus/aarch64/cortex_a720.S | 8 +++++++- lib/cpus/cpu-ops.mk | 7 ++++++- lib/cpus/errata_common.c | 8 ++++++++ 5 files changed, 30 insertions(+), 3 deletions(-) diff --git a/docs/design/cpu-specific-build-macros.rst b/docs/design/cpu-specific-build-macros.rst index 47fa95568..34fa2e933 100644 --- a/docs/design/cpu-specific-build-macros.rst +++ b/docs/design/cpu-specific-build-macros.rst @@ -982,6 +982,10 @@ For Cortex-A720, the following errata build flags are defined : Cortex-A720 CPU. This needs to be enabled for revisions r0p0 and r0p1. It is fixed in r0p2. +- ``ERRATA_A720_3699561``: This applies errata 3699561 workaround to + Cortex-A720 CPU. This needs to be enabled for revisions r0p0, r0p1 + and r0p2. It is still open. + DSU Errata Workarounds ---------------------- diff --git a/include/lib/cpus/aarch64/cortex_a720.h b/include/lib/cpus/aarch64/cortex_a720.h index 129c1ee33..670438f10 100644 --- a/include/lib/cpus/aarch64/cortex_a720.h +++ b/include/lib/cpus/aarch64/cortex_a720.h @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -38,4 +38,8 @@ #define CORTEX_A720_CPUPWRCTLR_EL1 S3_0_C15_C2_7 #define CORTEX_A720_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1) +#ifndef __ASSEMBLER__ +long check_erratum_cortex_a720_3699561(long cpu_rev); +#endif /* __ASSEMBLER__ */ + #endif /* CORTEX_A720_H */ diff --git a/lib/cpus/aarch64/cortex_a720.S b/lib/cpus/aarch64/cortex_a720.S index 9befb36eb..ab2c12f3f 100644 --- a/lib/cpus/aarch64/cortex_a720.S +++ b/lib/cpus/aarch64/cortex_a720.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2021-2024, Arm Limited. All rights reserved. + * Copyright (c) 2021-2025, Arm Limited. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -22,6 +22,8 @@ #error "Cortex A720 supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0" #endif +.global check_erratum_cortex_a720_3699561 + #if WORKAROUND_CVE_2022_23960 wa_cve_2022_23960_bhb_vector_table CORTEX_A720_BHB_LOOP_COUNT, cortex_a720 #endif /* WORKAROUND_CVE_2022_23960 */ @@ -72,6 +74,10 @@ workaround_reset_end cortex_a720, CVE(2022, 23960) check_erratum_chosen cortex_a720, CVE(2022, 23960), WORKAROUND_CVE_2022_23960 +add_erratum_entry cortex_a720, ERRATUM(3699561), ERRATA_A720_3699561, NO_APPLY_AT_RESET + +check_erratum_ls cortex_a720, ERRATUM(3699561), CPU_REV(0, 2) + cpu_reset_func_start cortex_a720 /* Disable speculative loads */ msr SSBS, xzr diff --git a/lib/cpus/cpu-ops.mk b/lib/cpus/cpu-ops.mk index 0e5e24c69..68a50fc0d 100644 --- a/lib/cpus/cpu-ops.mk +++ b/lib/cpus/cpu-ops.mk @@ -1010,12 +1010,17 @@ CPU_FLAG_LIST += ERRATA_A720_2926083 # to revisions r0p0 and r0p1. It is fixed in r0p2. CPU_FLAG_LIST += ERRATA_A720_2940794 +# Flag to apply erratum 3699561 workaround during context save/restore of +# ICH_VMCR_EL2 reg. This erratum applies to revisions r0p0, r0p1, r0p2 of +# the Cortex-A720 cpu and is still open. +CPU_FLAG_LIST += ERRATA_A720_3699561 + # Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0. # Applying the workaround results in higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_798953 # Flag to apply DSU erratum 936184. This erratum applies to DSUs containing -# the ACP interface and revision < r2p0. Applying the workaround results in +# the ACP interface and revision < r0p0. Applying the workaround results in # higher DSU power consumption on idle. CPU_FLAG_LIST += ERRATA_DSU_936184 diff --git a/lib/cpus/errata_common.c b/lib/cpus/errata_common.c index 08f878606..e5d14d509 100644 --- a/lib/cpus/errata_common.c +++ b/lib/cpus/errata_common.c @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include @@ -60,6 +61,13 @@ bool errata_ich_vmcr_el2_applies(void) break; #endif /* ERRATA_A715_3699560 */ +#if ERRATA_A720_3699561 + case EXTRACT_PARTNUM(CORTEX_A720_MIDR): + if (check_erratum_cortex_a720_3699561(cpu_get_rev_var()) == ERRATA_APPLIES) + return true;; + break; +#endif /* ERRATA_A720_3699561 */ + default: break; }