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rcar_gen3: E3 target: fix compilation issues

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Target builds but has not been tested.

Signed-off-by: ldts <jorge.ramirez.ortiz@gmail.com>
This commit is contained in:
ldts 2018-11-06 10:17:12 +01:00
parent d65895f4a8
commit 04d1f8dd49
4 changed files with 8 additions and 7 deletions
drivers
renesas/rcar/watchdog
swdt.c
staging/renesas/rcar/ddr/ddr_a
ddr_init_e3.cddr_init_e3.h
plat/renesas/rcar
bl2_cpg_init.c

4
drivers/renesas/rcar/watchdog/swdt.c
View file

@ -72,9 +72,9 @@ static void swdt_disable(void)
void rcar_swdt_init(void) void rcar_swdt_init(void)
{ {
uint32_t rmsk, val, sr; uint32_t rmsk, sr;
#if (RCAR_LSI != RCAR_E3) #if (RCAR_LSI != RCAR_E3)
uint32_t reg, product_cut, chk_data; uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR); reg = mmio_read_32(RCAR_PRR);
product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK); product_cut = reg & (RCAR_PRODUCT_MASK | RCAR_CUT_MASK);

6
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View file

@ -1046,7 +1046,7 @@ uint32_t recovery_from_backup_mode(void)
} else { } else {
NOTICE("[COLD_BOOT]"); NOTICE("[COLD_BOOT]");
} /* ddrBackup */ } /* ddrBackup */
err=dram_update_boot_status(ddrBackup); err=rcar_dram_update_boot_status(ddrBackup);
if(err){ if(err){
NOTICE("[BOOT_STATUS_UPDATE_ERROR]"); NOTICE("[BOOT_STATUS_UPDATE_ERROR]");
return INITDRAM_ERR_I; return INITDRAM_ERR_I;
@ -1500,7 +1500,7 @@ if (pdqsr_ctl == 1){
/******************************************************************************* /*******************************************************************************
* DDR Initialize entry for IPL * DDR Initialize entry for IPL
******************************************************************************/ ******************************************************************************/
int32_t InitDram(void) int32_t rcar_dram_init(void)
{ {
uint32_t dataL; uint32_t dataL;
uint32_t failcount; uint32_t failcount;
@ -1516,7 +1516,7 @@ int32_t InitDram(void)
NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION); NOTICE("BL2: DDR1856(%s)", RCAR_E3_DDR_VERSION);
} /* ddr */ } /* ddr */
dram_get_boot_status(&ddrBackup); rcar_dram_get_boot_status(&ddrBackup);
if(ddrBackup==DRAM_BOOT_STATUS_WARM){ if(ddrBackup==DRAM_BOOT_STATUS_WARM){
dataL=recovery_from_backup_mode(); /* WARM boot */ dataL=recovery_from_backup_mode(); /* WARM boot */

2
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
View file

@ -24,7 +24,7 @@
#endif #endif
#endif #endif
extern int32_t InitDram(void); extern int32_t rcar_dram_init(void);
#define INITDRAM_OK (0) #define INITDRAM_OK (0)
#define INITDRAM_NG (0xffffffff) #define INITDRAM_NG (0xffffffff)
#define INITDRAM_ERR_I (0xffffffff) #define INITDRAM_ERR_I (0xffffffff)

3
plat/renesas/rcar/bl2_cpg_init.c
View file

@ -42,7 +42,8 @@ static void bl2_secure_cpg_init(void)
uint32_t stop_cr2, reset_cr2; uint32_t stop_cr2, reset_cr2;
#if (RCAR_LSI == RCAR_E3) #if (RCAR_LSI == RCAR_E3)
reset_cr2 = 0x10000000U stop_cr2 = 0xEFFFFFFFU; reset_cr2 = 0x10000000U;
stop_cr2 = 0xEFFFFFFFU;
#else #else
reset_cr2 = 0x14000000U; reset_cr2 = 0x14000000U;
stop_cr2 = 0xEBFFFFFFU; stop_cr2 = 0xEBFFFFFFU;