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Helper macro to create MAIR encodings

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This patch provides helper macros for both Device and Normal memory MAIR
encodings as defined by the ARM Architecture Reference Manual for ARMv8-A
(ARM DDI0487B.A).

Change-Id: I5faae7f2cf366390ad4ba1d9253c6f3b60fd5e20
Signed-off-by: David Cunado <david.cunado@arm.com>
This commit is contained in:
Isla Mitchell 2017-07-21 14:44:36 +01:00 • committed by David Cunado
parent 8121bc0f9f
commit 04880e3fe6
3 changed files with 105 additions and 3 deletions
include/lib
aarch32
arch.h
aarch64
arch.h
xlat_tables
xlat_tables_defs.h

51
include/lib/aarch32/arch.h
View file

@ -7,6 +7,8 @@
#ifndef __ARCH_H__
#define __ARCH_H__
#include <utils_def.h>
/*******************************************************************************
* MIDR bit definitions
******************************************************************************/
@ -459,4 +461,53 @@
#define ICC_ASGI1R_EL1_64 p15, 1, c12
#define ICC_SGI0R_EL1_64 p15, 2, c12
/*******************************************************************************
* Definitions of MAIR encodings for device and normal memory
******************************************************************************/
/*
* MAIR encodings for device memory attributes.
*/
#define MAIR_DEV_nGnRnE U(0x0)
#define MAIR_DEV_nGnRE U(0x4)
#define MAIR_DEV_nGRE U(0x8)
#define MAIR_DEV_GRE U(0xc)
/*
* MAIR encodings for normal memory attributes.
*
* Cache Policy
* WT: Write Through
* WB: Write Back
* NC: Non-Cacheable
*
* Transient Hint
* NTR: Non-Transient
* TR: Transient
*
* Allocation Policy
* RA: Read Allocate
* WA: Write Allocate
* RWA: Read and Write Allocate
* NA: No Allocation
*/
#define MAIR_NORM_WT_TR_WA U(0x1)
#define MAIR_NORM_WT_TR_RA U(0x2)
#define MAIR_NORM_WT_TR_RWA U(0x3)
#define MAIR_NORM_NC U(0x4)
#define MAIR_NORM_WB_TR_WA U(0x5)
#define MAIR_NORM_WB_TR_RA U(0x6)
#define MAIR_NORM_WB_TR_RWA U(0x7)
#define MAIR_NORM_WT_NTR_NA U(0x8)
#define MAIR_NORM_WT_NTR_WA U(0x9)
#define MAIR_NORM_WT_NTR_RA U(0xa)
#define MAIR_NORM_WT_NTR_RWA U(0xb)
#define MAIR_NORM_WB_NTR_NA U(0xc)
#define MAIR_NORM_WB_NTR_WA U(0xd)
#define MAIR_NORM_WB_NTR_RA U(0xe)
#define MAIR_NORM_WB_NTR_RWA U(0xf)
#define MAIR_NORM_OUTER_SHIFT 4
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
#endif /* __ARCH_H__ */

49
include/lib/aarch64/arch.h
View file

@ -504,4 +504,53 @@
#define PMCR_EL0_N_MASK U(0x1f)
#define PMCR_EL0_N_BITS (PMCR_EL0_N_MASK << PMCR_EL0_N_SHIFT)
/*******************************************************************************
* Definitions of MAIR encodings for device and normal memory
******************************************************************************/
/*
* MAIR encodings for device memory attributes.
*/
#define MAIR_DEV_nGnRnE ULL(0x0)
#define MAIR_DEV_nGnRE ULL(0x4)
#define MAIR_DEV_nGRE ULL(0x8)
#define MAIR_DEV_GRE ULL(0xc)
/*
* MAIR encodings for normal memory attributes.
*
* Cache Policy
* WT: Write Through
* WB: Write Back
* NC: Non-Cacheable
*
* Transient Hint
* NTR: Non-Transient
* TR: Transient
*
* Allocation Policy
* RA: Read Allocate
* WA: Write Allocate
* RWA: Read and Write Allocate
* NA: No Allocation
*/
#define MAIR_NORM_WT_TR_WA ULL(0x1)
#define MAIR_NORM_WT_TR_RA ULL(0x2)
#define MAIR_NORM_WT_TR_RWA ULL(0x3)
#define MAIR_NORM_NC ULL(0x4)
#define MAIR_NORM_WB_TR_WA ULL(0x5)
#define MAIR_NORM_WB_TR_RA ULL(0x6)
#define MAIR_NORM_WB_TR_RWA ULL(0x7)
#define MAIR_NORM_WT_NTR_NA ULL(0x8)
#define MAIR_NORM_WT_NTR_WA ULL(0x9)
#define MAIR_NORM_WT_NTR_RA ULL(0xa)
#define MAIR_NORM_WT_NTR_RWA ULL(0xb)
#define MAIR_NORM_WB_NTR_NA ULL(0xc)
#define MAIR_NORM_WB_NTR_WA ULL(0xd)
#define MAIR_NORM_WB_NTR_RA ULL(0xe)
#define MAIR_NORM_WB_NTR_RWA ULL(0xf)
#define MAIR_NORM_OUTER_SHIFT 4
#define MAKE_MAIR_NORMAL_MEMORY(inner, outer) ((inner) | ((outer) << MAIR_NORM_OUTER_SHIFT))
#endif /* __ARCH_H__ */

8
include/lib/xlat_tables/xlat_tables_defs.h
View file

@ -7,6 +7,7 @@
#ifndef __XLAT_TABLES_DEFS_H__
#define __XLAT_TABLES_DEFS_H__
#include <arch.h>
#include <utils_def.h>
/* Miscellaneous MMU related constants */
@ -96,12 +97,13 @@
#define ATTR_DEVICE_INDEX U(0x1)
#define ATTR_IWBWA_OWBWA_NTR_INDEX U(0x0)
#define LOWER_ATTRS(x) (((x) & U(0xfff)) << 2)
/* Normal Memory, Outer Write-Through non-transient, Inner Non-cacheable */
#define ATTR_NON_CACHEABLE U(0x44)
#define ATTR_NON_CACHEABLE MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_NC, MAIR_NORM_NC)
/* Device-nGnRE */
#define ATTR_DEVICE U(0x4)
#define ATTR_DEVICE MAIR_DEV_nGnRE
/* Normal Memory, Outer Write-Back non-transient, Inner Write-Back non-transient */
#define ATTR_IWBWA_OWBWA_NTR U(0xff)
#define ATTR_IWBWA_OWBWA_NTR MAKE_MAIR_NORMAL_MEMORY(MAIR_NORM_WB_NTR_RWA, MAIR_NORM_WB_NTR_RWA)
#define MAIR_ATTR_SET(attr, index) ((attr) << ((index) << 3))
#define ATTR_INDEX_MASK U(0x3)
#define ATTR_INDEX_GET(attr) (((attr) >> 2) & ATTR_INDEX_MASK)