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Merge "Add Cortex_A78C CPU lib" into integration
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commit
045b209cc2
4 changed files with 93 additions and 2 deletions
24
include/lib/cpus/aarch64/cortex_a78c.h
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24
include/lib/cpus/aarch64/cortex_a78c.h
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A78C_H
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#define CORTEX_A78C_H
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#define CORTEX_A78C_MIDR U(0x410FD4B1)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A78C_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_A78C_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT U(1)
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#endif /* CORTEX_A78C_H */
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65
lib/cpus/aarch64/cortex_a78c.S
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lib/cpus/aarch64/cortex_a78c.S
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_a78c.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "cortex_a78c must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_a78c_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_A78C_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A78C_CPUPWRCTLR_EL1_CORE_PWRDN_EN_BIT
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msr CORTEX_A78C_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a78c_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex A78C. Must follow AAPCS.
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*/
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func cortex_a78c_errata_report
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ret
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endfunc cortex_a78c_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides cortex_a78c specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a78c_regs, "aS"
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cortex_a78c_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a78c_cpu_reg_dump
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adr x6, cortex_a78c_regs
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mrs x8, CORTEX_A78C_CPUECTLR_EL1
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ret
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endfunc cortex_a78c_cpu_reg_dump
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declare_cpu_ops cortex_a78c, CORTEX_A78C_MIDR, \
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CPU_NO_RESET_FUNC, \
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cortex_a78c_core_pwr_dwn
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@ -70,7 +70,8 @@ else
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_matterhorn.S \
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lib/cpus/aarch64/cortex_matterhorn.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu_elp.S
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lib/cpus/aarch64/cortex_makalu_elp.S \
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lib/cpus/aarch64/cortex_a78c.S
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# AArch64/AArch32 cores
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# AArch64/AArch32 cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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@ -136,7 +136,8 @@ else
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_makalu_elp.S \
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lib/cpus/aarch64/cortex_makalu_elp.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65ae.S
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_a78c.S
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endif
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endif
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# AArch64/AArch32 cores
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# AArch64/AArch32 cores
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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