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feat(tc): bind SMMU-700 with DPU on TC3
TC3 adds a new SMMU-700 specifically for the DPU. This is used as the DPU SMMU instead of the existing SMMU used for the DPU. Update the device tree to reflect this. Change-Id: I865140f8f53bceaa8849f6583190b240eeee0539 Signed-off-by: Jackson Cooper-Driver <jackson.cooper-driver@arm.com> Signed-off-by: Leo Yan <leo.yan@arm.com>
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2 changed files with 23 additions and 0 deletions
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@ -516,6 +516,18 @@
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status = "disabled";
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};
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smmu_700_dpu: iommu@4002a00000 {
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#iommu-cells = <1>;
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compatible = "arm,smmu-v3";
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reg = <HI(0x4002a00000) LO(0x4002a00000) 0x0 0x5000000>;
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interrupts = <GIC_SPI 481 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 482 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 483 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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dma-coherent;
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status = "disabled";
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};
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dp0: display@DPU_ADDR {
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#address-cells = <1>;
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#size-cells = <0>;
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11
fdts/tc3.dts
11
fdts/tc3.dts
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@ -90,8 +90,19 @@
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smmu_700: iommu@3f000000 {
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status = "okay";
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};
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smmu_700_dpu: iommu@4002a00000 {
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status = "okay";
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};
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#endif
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dp0: display@DPU_ADDR {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700_dpu 0x000>, <&smmu_700_dpu 0x100>,
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<&smmu_700_dpu 0x200>, <&smmu_700_dpu 0x600>;
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#endif
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};
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gpu: gpu@2d000000 {
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#if TARGET_FLAVOUR_FVP
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iommus = <&smmu_700 0x200>;
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