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Rename GICv3 interrupt group macros

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This patch renames the GICv3 interrupt group macros from
INT_TYPE_G0, INT_TYPE_G1S and INT_TYPE_G1NS to INTR_GROUP0,
INTR_GROUP1S and INTR_GROUP1NS respectively.

Change-Id: I40c66f589ce6234fa42205adcd91f7d6ad8f33d4
This commit is contained in:
Soby Mathew 2015-12-03 14:12:54 +00:00
parent f3974ea5b1
commit 03ffb6bdef
3 changed files with 18 additions and 18 deletions
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8
drivers/arm/gic/v3/gicv3_helpers.c
View file

@ -312,7 +312,7 @@ void gicv3_secure_spis_configure(uintptr_t gicd_base,
unsigned int index, irq_num; unsigned int index, irq_num;
uint64_t gic_affinity_val; uint64_t gic_affinity_val;
assert((int_grp == INT_TYPE_G1S) || (int_grp == INT_TYPE_G0)); assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
assert(num_ints ? (uintptr_t)sec_intr_list : 1); assert(num_ints ? (uintptr_t)sec_intr_list : 1);
@ -324,7 +324,7 @@ void gicv3_secure_spis_configure(uintptr_t gicd_base,
gicd_clr_igroupr(gicd_base, irq_num); gicd_clr_igroupr(gicd_base, irq_num);
/* Configure this interrupt as G0 or a G1S interrupt */ /* Configure this interrupt as G0 or a G1S interrupt */
if (int_grp == INT_TYPE_G1S) if (int_grp == INTR_GROUP1S)
gicd_set_igrpmodr(gicd_base, irq_num); gicd_set_igrpmodr(gicd_base, irq_num);
else else
gicd_clr_igrpmodr(gicd_base, irq_num); gicd_clr_igrpmodr(gicd_base, irq_num);
@ -386,7 +386,7 @@ void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
{ {
unsigned int index, irq_num; unsigned int index, irq_num;
assert((int_grp == INT_TYPE_G1S) || (int_grp == INT_TYPE_G0)); assert((int_grp == INTR_GROUP1S) || (int_grp == INTR_GROUP0));
/* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */ /* If `num_ints` is not 0, ensure that `sec_intr_list` is not NULL */
assert(num_ints ? (uintptr_t)sec_intr_list : 1); assert(num_ints ? (uintptr_t)sec_intr_list : 1);
@ -398,7 +398,7 @@ void gicv3_secure_ppi_sgi_configure(uintptr_t gicr_base,
gicr_clr_igroupr0(gicr_base, irq_num); gicr_clr_igroupr0(gicr_base, irq_num);
/* Configure this interrupt as G0 or a G1S interrupt */ /* Configure this interrupt as G0 or a G1S interrupt */
if (int_grp == INT_TYPE_G1S) if (int_grp == INTR_GROUP1S)
gicr_set_igrpmodr0(gicr_base, irq_num); gicr_set_igrpmodr0(gicr_base, irq_num);
else else
gicr_clr_igrpmodr0(gicr_base, irq_num); gicr_clr_igrpmodr0(gicr_base, irq_num);

22
drivers/arm/gic/v3/gicv3_main.c
View file

@ -144,13 +144,13 @@ void gicv3_distif_init(void)
gicv3_secure_spis_configure(driver_data->gicd_base, gicv3_secure_spis_configure(driver_data->gicd_base,
driver_data->g1s_interrupt_num, driver_data->g1s_interrupt_num,
driver_data->g1s_interrupt_array, driver_data->g1s_interrupt_array,
INT_TYPE_G1S); INTR_GROUP1S);
/* Configure the G0 SPIs */ /* Configure the G0 SPIs */
gicv3_secure_spis_configure(driver_data->gicd_base, gicv3_secure_spis_configure(driver_data->gicd_base,
driver_data->g0_interrupt_num, driver_data->g0_interrupt_num,
driver_data->g0_interrupt_array, driver_data->g0_interrupt_array,
INT_TYPE_G0); INTR_GROUP0);
/* Enable the secure SPIs now that they have been configured */ /* Enable the secure SPIs now that they have been configured */
gicd_set_ctlr(driver_data->gicd_base, gicd_set_ctlr(driver_data->gicd_base,
@ -186,13 +186,13 @@ void gicv3_rdistif_init(unsigned int proc_num)
gicv3_secure_ppi_sgi_configure(gicr_base, gicv3_secure_ppi_sgi_configure(gicr_base,
driver_data->g1s_interrupt_num, driver_data->g1s_interrupt_num,
driver_data->g1s_interrupt_array, driver_data->g1s_interrupt_array,
INT_TYPE_G1S); INTR_GROUP1S);
/* Configure the G0 SGIs/PPIs */ /* Configure the G0 SGIs/PPIs */
gicv3_secure_ppi_sgi_configure(gicr_base, gicv3_secure_ppi_sgi_configure(gicr_base,
driver_data->g0_interrupt_num, driver_data->g0_interrupt_num,
driver_data->g0_interrupt_array, driver_data->g0_interrupt_array,
INT_TYPE_G0); INTR_GROUP0);
} }
/******************************************************************************* /*******************************************************************************
@ -332,9 +332,9 @@ unsigned int gicv3_get_pending_interrupt_type(void)
* this interrupt has been configured under by the interrupt controller i.e. * this interrupt has been configured under by the interrupt controller i.e.
* group0 or group1 Secure / Non Secure. The return value can be one of the * group0 or group1 Secure / Non Secure. The return value can be one of the
* following : * following :
* INT_TYPE_G0 : The interrupt type is a Secure Group 0 interrupt * INTR_GROUP0 : The interrupt type is a Secure Group 0 interrupt
* INT_TYPE_G1S : The interrupt type is a Secure Group 1 secure interrupt * INTR_GROUP1S : The interrupt type is a Secure Group 1 secure interrupt
* INT_TYPE_G1NS: The interrupt type is a Secure Group 1 non secure * INTR_GROUP1NS: The interrupt type is a Secure Group 1 non secure
* interrupt. * interrupt.
******************************************************************************/ ******************************************************************************/
unsigned int gicv3_get_interrupt_type(unsigned int id, unsigned int gicv3_get_interrupt_type(unsigned int id,
@ -352,7 +352,7 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
/* All LPI interrupts are Group 1 non secure */ /* All LPI interrupts are Group 1 non secure */
if (id >= MIN_LPI_ID) if (id >= MIN_LPI_ID)
return INT_TYPE_G1NS; return INTR_GROUP1NS;
if (id < MIN_SPI_ID) { if (id < MIN_SPI_ID) {
assert(driver_data->rdistif_base_addrs); assert(driver_data->rdistif_base_addrs);
@ -370,12 +370,12 @@ unsigned int gicv3_get_interrupt_type(unsigned int id,
* interrupt * interrupt
*/ */
if (igroup) if (igroup)
return INT_TYPE_G1NS; return INTR_GROUP1NS;
/* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */ /* If the GRPMOD bit is set, then it is a Group 1 Secure interrupt */
if (grpmodr) if (grpmodr)
return INT_TYPE_G1S; return INTR_GROUP1S;
/* Else it is a Group 0 Secure interrupt */ /* Else it is a Group 0 Secure interrupt */
return INT_TYPE_G0; return INTR_GROUP0;
} }

6
include/drivers/arm/gicv3.h
View file

@ -35,9 +35,9 @@
* GICv3 miscellaneous definitions * GICv3 miscellaneous definitions
******************************************************************************/ ******************************************************************************/
/* Interrupt group definitions */ /* Interrupt group definitions */
#define INT_TYPE_G1S 0 #define INTR_GROUP1S 0
#define INT_TYPE_G0 1 #define INTR_GROUP0 1
#define INT_TYPE_G1NS 2 #define INTR_GROUP1NS 2
/* Interrupt IDs reported by the HPPIR and IAR registers */ /* Interrupt IDs reported by the HPPIR and IAR registers */
#define PENDING_G1S_INTID 1020 #define PENDING_G1S_INTID 1020