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fix(arm-drivers): add missing curly braces

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This corrects the MISRA violation C2012-15.6:
The body of an iteration-statement or a selection-statement shall
be a compound-statement.
Enclosed statement body within the curly braces.

Change-Id: I66f957467bdee13052847f3e8c5ad6ae258c4222
Signed-off-by: Nithin G <nithing@amd.com>
Signed-off-by: Maheedhar Bollapalli <maheedharsai.bollapalli@amd.com>
This commit is contained in:
Maheedhar Bollapalli 2024-04-25 10:57:33 +05:30
parent 0eeda638a8
commit 03c6bb0e38
3 changed files with 24 additions and 21 deletions

6
drivers/arm/cci/cci.c
View file

@ -153,8 +153,9 @@ void cci_enable_snoop_dvm_reqs(unsigned int master_id)
dsbish();
/* Wait for the dust to settle down */
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) {
;
}
}
void cci_disable_snoop_dvm_reqs(unsigned int master_id)
@ -180,7 +181,8 @@ void cci_disable_snoop_dvm_reqs(unsigned int master_id)
dsbish();
/* Wait for the dust to settle down */
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U)
while ((mmio_read_32(cci_base + STATUS_REG) & CHANGE_PENDING_BIT) != 0U) {
;
}
}

31
drivers/arm/gic/v2/gicv2_helpers.c
View file

@ -101,18 +101,19 @@ void gicv2_spis_configure_defaults(uintptr_t gicd_base)
* Treat all SPIs as G1NS by default. The number of interrupts is
* calculated as 32 * (IT_LINES + 1). We do 32 at a time.
*/
for (index = MIN_SPI_ID; index < num_ints; index += 32U)
for (index = MIN_SPI_ID; index < num_ints; index += 32U) {
gicd_write_igroupr(gicd_base, index, ~0U);
}
/* Setup the default SPI priorities doing four at a time */
for (index = MIN_SPI_ID; index < num_ints; index += 4U)
for (index = MIN_SPI_ID; index < num_ints; index += 4U) {
gicd_write_ipriorityr(gicd_base,
index,
GICD_IPRIORITYR_DEF_VAL);
}
/* Treat all SPIs as level triggered by default, 16 at a time */
for (index = MIN_SPI_ID; index < num_ints; index += 16U)
for (index = MIN_SPI_ID; index < num_ints; index += 16U) {
gicd_write_icfgr(gicd_base, index, 0U);
}
}
/*******************************************************************************
@ -126,15 +127,15 @@ void gicv2_secure_spis_configure_props(uintptr_t gicd_base,
const interrupt_prop_t *prop_desc;
/* Make sure there's a valid property array */
if (interrupt_props_num != 0U)
if (interrupt_props_num != 0U) {
assert(interrupt_props != NULL);
}
for (i = 0; i < interrupt_props_num; i++) {
prop_desc = &interrupt_props[i];
if (prop_desc->intr_num < MIN_SPI_ID)
if (prop_desc->intr_num < MIN_SPI_ID) {
continue;
}
/* Configure this interrupt as a secure interrupt */
assert(prop_desc->intr_grp == GICV2_INTR_GROUP0);
gicd_clr_igroupr(gicd_base, prop_desc->intr_num);
@ -168,9 +169,9 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
const interrupt_prop_t *prop_desc;
/* Make sure there's a valid property array */
if (interrupt_props_num != 0U)
if (interrupt_props_num != 0U) {
assert(interrupt_props != NULL);
}
/*
* Disable all SGIs (imp. def.)/PPIs before configuring them. This is a
* more scalable approach as it avoids clearing the enable bits in the
@ -179,15 +180,15 @@ void gicv2_secure_ppi_sgi_setup_props(uintptr_t gicd_base,
gicd_write_icenabler(gicd_base, 0U, ~0U);
/* Setup the default PPI/SGI priorities doing four at a time */
for (i = 0U; i < MIN_SPI_ID; i += 4U)
for (i = 0U; i < MIN_SPI_ID; i += 4U) {
gicd_write_ipriorityr(gicd_base, i, GICD_IPRIORITYR_DEF_VAL);
}
for (i = 0U; i < interrupt_props_num; i++) {
prop_desc = &interrupt_props[i];
if (prop_desc->intr_num >= MIN_SPI_ID)
if (prop_desc->intr_num >= MIN_SPI_ID) {
continue;
}
/* Configure this interrupt as a secure interrupt */
assert(prop_desc->intr_grp == GICV2_INTR_GROUP0);

8
drivers/arm/gic/v2/gicv2_main.c
View file

@ -220,9 +220,9 @@ unsigned int gicv2_get_pending_interrupt_id(void)
* Find out which non-secure interrupt it is under the assumption that
* the GICC_CTLR.AckCtl bit is 0.
*/
if (id == PENDING_G1_INTID)
if (id == PENDING_G1_INTID) {
id = gicc_read_ahppir(driver_data->gicc_base) & INT_ID_MASK;
}
return id;
}
@ -301,9 +301,9 @@ void gicv2_set_pe_target_mask(unsigned int proc_num)
assert(proc_num < driver_data->target_masks_num);
/* Return if the target mask is already populated */
if (driver_data->target_masks[proc_num] != 0U)
if (driver_data->target_masks[proc_num] != 0U) {
return;
}
/*
* Update target register corresponding to this CPU and flush for it to
* be visible to other CPUs.