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Merge pull request #248 from jcastillo-arm/jc/tf-issues/212_1
Allow BL3-2 to be loaded into the secure region of DRAM
This commit is contained in:
danh-arm
commit
03b2370386
9 changed files with 126 additions and 39 deletions
2
Makefile
2
Makefile
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@ -363,7 +363,7 @@ $(eval PREREQUISITES := $(1).d)
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$(1) : $(2)
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@echo " PP $$<"
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$$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
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$$(Q)$$(AS) $$(ASFLAGS) -P -E -D__LINKER__ -o $$@ $$<
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$(PREREQUISITES) : $(2)
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@echo " DEPS $$@"
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@ -1269,14 +1269,19 @@ The following list describes the memory layout on the FVP:
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* BL2 is loaded below BL3-1.
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* The TSP is loaded as the BL3-2 image at the base of either the Trusted
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SRAM or Trusted DRAM. When loaded into Trusted SRAM, its NOBITS sections
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are allowed to overlay BL2.
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* BL3-2 can be loaded in one of the following locations:
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This memory layout is designed to give the BL3-2 image as much memory as
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possible when it is loaded into Trusted SRAM. Depending on the location of the
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TSP, it will result in different memory maps, illustrated by the following
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diagrams.
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* Trusted SRAM
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* Trusted DRAM
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* Secure region of DRAM (top 16MB of DRAM configured by the TrustZone
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controller)
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When BL3-2 is loaded into Trusted SRAM, its NOBITS sections are allowed to
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overlay BL2. This memory layout is designed to give the BL3-2 image as much
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memory as possible when it is loaded into Trusted SRAM.
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The location of the BL3-2 image will result in different memory maps. This is
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illustrated in the following diagrams using the TSP as an example.
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**TSP in Trusted SRAM (default option):**
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@ -1324,8 +1329,37 @@ diagrams.
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| BL1 (ro) |
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0x00000000 +----------+
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Loading the TSP image in Trusted DRAM doesn't change the memory layout of the
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other boot loader images in Trusted SRAM.
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**TSP in the TZC-Secured DRAM:**
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DRAM
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0xffffffff +----------+
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| BL3-2 | (secure)
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0xff000000 +----------+
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| |
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: : (non-secure)
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| |
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0x80000000 +----------+
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Trusted SRAM
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0x04040000 +----------+ loaded by BL2 ------------------
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| BL1 (rw) | <<<<<<<<<<<<< | BL3-1 NOBITS |
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|----------| <<<<<<<<<<<<< |----------------|
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| | <<<<<<<<<<<<< | BL3-1 PROGBITS |
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|----------| ------------------
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| BL2 |
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|----------|
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| |
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0x04001000 +----------+
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| Shared |
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0x04000000 +----------+
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Trusted ROM
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0x04000000 +----------+
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| BL1 (ro) |
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0x00000000 +----------+
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Moving the TSP image out of the Trusted SRAM doesn't change the memory layout
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of the other boot loader images in Trusted SRAM.
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#### Memory layout on Juno ARM development platform
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@ -259,8 +259,9 @@ performed.
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#### FVP specific build options
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* `FVP_TSP_RAM_LOCATION`: location of the TSP binary. Options:
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- `tsram` (default) : Trusted SRAM
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- `tsram` : Trusted SRAM (default option)
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- `tdram` : Trusted DRAM
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- `dram` : Secure region in DRAM (configured by the TrustZone controller)
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For a better understanding of FVP options, the FVP memory map is explained in
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the [Firmware Design].
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@ -66,8 +66,8 @@ plat_config_t plat_config;
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DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_DRAM1 MAP_REGION_FLAT(DRAM1_BASE, \
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DRAM1_SIZE, \
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#define MAP_DRAM1_NS MAP_REGION_FLAT(DRAM1_NS_BASE, \
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DRAM1_NS_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_TSP_SEC_MEM MAP_REGION_FLAT(TSP_SEC_MEM_BASE, \
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@ -94,7 +94,7 @@ const mmap_region_t fvp_mmap[] = {
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MAP_FLASH0,
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MAP_DEVICE0,
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MAP_DEVICE1,
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MAP_DRAM1,
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MAP_DRAM1_NS,
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MAP_TSP_SEC_MEM,
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{0}
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};
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@ -284,8 +284,8 @@ void bl2_plat_get_bl32_meminfo(meminfo_t *bl32_meminfo)
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******************************************************************************/
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void bl2_plat_get_bl33_meminfo(meminfo_t *bl33_meminfo)
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{
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bl33_meminfo->total_base = DRAM_BASE;
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bl33_meminfo->total_size = DRAM_SIZE - DRAM1_SEC_SIZE;
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bl33_meminfo->free_base = DRAM_BASE;
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bl33_meminfo->free_size = DRAM_SIZE - DRAM1_SEC_SIZE;
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bl33_meminfo->total_base = DRAM1_NS_BASE;
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bl33_meminfo->total_size = DRAM1_NS_SIZE;
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bl33_meminfo->free_base = DRAM1_NS_BASE;
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bl33_meminfo->free_size = DRAM1_NS_SIZE;
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}
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@ -36,8 +36,29 @@
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#define FVP_PRIMARY_CPU 0x0
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/* Memory location options for TSP */
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#define FVP_IN_TRUSTED_SRAM 0
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#define FVP_IN_TRUSTED_DRAM 1
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#define FVP_TRUSTED_SRAM_ID 0
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#define FVP_TRUSTED_DRAM_ID 1
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#define FVP_DRAM_ID 2
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/*
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* Some of the definitions in this file use the 'ull' suffix in order to avoid
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* subtle integer overflow errors due to implicit integer type promotion when
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* working with 32-bit values.
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*
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* The TSP linker script includes some of these definitions to define the BL3-2
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* memory map, but the GNU LD does not support the 'ull' suffix, causing the
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* build process to fail. To solve this problem, the auxiliary macro MAKE_ULL(x)
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* will add the 'ull' suffix only when the macro __LINKER__ is not defined
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* (__LINKER__ is defined in the command line to preprocess the linker script).
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* Constants in the linker script will not have the 'ull' suffix, but this is
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* not a problem since the linker evaluates all constant expressions to 64 bit
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* (assuming the target architecture is 64 bit).
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*/
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#ifndef __LINKER__
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#define MAKE_ULL(x) x##ull
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#else
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#define MAKE_ULL(x) x
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#endif
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/*******************************************************************************
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* FVP memory map related constants
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@ -79,16 +100,24 @@
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#define NSRAM_BASE 0x2e000000
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#define NSRAM_SIZE 0x10000
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#define DRAM1_BASE 0x80000000ull
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#define DRAM1_SIZE 0x80000000ull
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#define DRAM1_BASE MAKE_ULL(0x80000000)
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#define DRAM1_SIZE MAKE_ULL(0x80000000)
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#define DRAM1_END (DRAM1_BASE + DRAM1_SIZE - 1)
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#define DRAM1_SEC_SIZE 0x01000000ull
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/* Define the top 16 MB of DRAM1 as secure */
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#define DRAM1_SEC_SIZE MAKE_ULL(0x01000000)
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#define DRAM1_SEC_BASE (DRAM1_BASE + DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_SEC_END (DRAM1_SEC_BASE + DRAM1_SEC_SIZE - 1)
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#define DRAM1_NS_BASE DRAM1_BASE
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#define DRAM1_NS_SIZE (DRAM1_SIZE - DRAM1_SEC_SIZE)
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#define DRAM1_NS_END (DRAM1_NS_BASE + DRAM1_NS_SIZE - 1)
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#define DRAM_BASE DRAM1_BASE
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#define DRAM_SIZE DRAM1_SIZE
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#define DRAM2_BASE 0x880000000ull
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#define DRAM2_SIZE 0x780000000ull
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#define DRAM2_BASE MAKE_ULL(0x880000000)
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#define DRAM2_SIZE MAKE_ULL(0x780000000)
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#define DRAM2_END (DRAM2_BASE + DRAM2_SIZE - 1)
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#define PCIE_EXP_BASE 0x40000000
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@ -89,16 +89,17 @@ void fvp_security_setup(void)
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* Allow only non-secure access to all DRAM to supported devices.
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* Give access to the CPUs and Virtio. Some devices
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* would normally use the default ID so allow that too. We use
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* two regions to cover the blocks of physical memory in the FVPs.
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* two regions to cover the blocks of physical memory in the FVPs
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* plus one region to reserve some memory as secure.
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*
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* Software executing in the secure state, such as a secure
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* boot-loader, can access the DRAM by using the NS attributes in
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* the MMU translation tables and descriptors.
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*/
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/* Set to cover the first block of DRAM */
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/* Region 1 set to cover the Non-Secure DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 1,
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DRAM1_BASE, DRAM1_END - DRAM1_SEC_SIZE,
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DRAM1_NS_BASE, DRAM1_NS_END,
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TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
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@ -106,14 +107,14 @@ void fvp_security_setup(void)
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_VIRTIO_OLD));
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/* Set to cover the secure reserved region */
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tzc_configure_region(FILTER_SHIFT(0), 3,
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(DRAM1_END - DRAM1_SEC_SIZE) + 1 , DRAM1_END,
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/* Region 2 set to cover the Secure DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 2,
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DRAM1_SEC_BASE, DRAM1_SEC_END,
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TZC_REGION_S_RDWR,
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0x0);
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/* Set to cover the second block of DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 2,
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/* Region 3 set to cover the second block of DRAM */
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tzc_configure_region(FILTER_SHIFT(0), 3,
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DRAM2_BASE, DRAM2_END, TZC_REGION_S_NONE,
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_DEFAULT) |
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TZC_REGION_ACCESS_RDWR(FVP_NSAID_PCI) |
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@ -128,19 +128,25 @@
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* BL32 specific defines.
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******************************************************************************/
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/*
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* On FVP, the TSP can execute either from Trusted SRAM or Trusted DRAM.
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* On FVP, the TSP can execute from Trusted SRAM, Trusted DRAM or the DRAM
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* region secured by the TrustZone controller.
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*/
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#if FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_SRAM
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#if FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_SRAM_ID
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_SRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_SRAM_SIZE
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# define TSP_PROGBITS_LIMIT BL2_BASE
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# define BL32_BASE FVP_TRUSTED_SRAM_BASE
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# define BL32_LIMIT BL31_BASE
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_IN_TRUSTED_DRAM
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_TRUSTED_DRAM_ID
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# define TSP_SEC_MEM_BASE FVP_TRUSTED_DRAM_BASE
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# define TSP_SEC_MEM_SIZE FVP_TRUSTED_DRAM_SIZE
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# define BL32_BASE FVP_TRUSTED_DRAM_BASE
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# define BL32_LIMIT (FVP_TRUSTED_DRAM_BASE + (1 << 21))
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#elif FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
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# define TSP_SEC_MEM_BASE DRAM1_SEC_BASE
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# define TSP_SEC_MEM_SIZE DRAM1_SEC_SIZE
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# define BL32_BASE DRAM1_SEC_BASE
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# define BL32_LIMIT (DRAM1_SEC_BASE + DRAM1_SEC_SIZE)
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#else
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# error "Unsupported FVP_TSP_RAM_LOCATION_ID value"
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#endif
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@ -154,7 +160,21 @@
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* Platform specific page table and MMU setup constants
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******************************************************************************/
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#define ADDR_SPACE_SIZE (1ull << 32)
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#define MAX_XLAT_TABLES 2
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#if IMAGE_BL1
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# define MAX_XLAT_TABLES 2
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#elif IMAGE_BL2
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# define MAX_XLAT_TABLES 3
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#elif IMAGE_BL31
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# define MAX_XLAT_TABLES 2
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#elif IMAGE_BL32
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# if FVP_TSP_RAM_LOCATION_ID == FVP_DRAM_ID
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# define MAX_XLAT_TABLES 3
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# else
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# define MAX_XLAT_TABLES 2
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# endif
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#endif
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#define MAX_MMAP_REGIONS 16
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/*******************************************************************************
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@ -32,9 +32,11 @@
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# Trusted SRAM is the default.
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FVP_TSP_RAM_LOCATION := tsram
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ifeq (${FVP_TSP_RAM_LOCATION}, tsram)
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FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_SRAM
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FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_SRAM_ID
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else ifeq (${FVP_TSP_RAM_LOCATION}, tdram)
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FVP_TSP_RAM_LOCATION_ID := FVP_IN_TRUSTED_DRAM
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FVP_TSP_RAM_LOCATION_ID := FVP_TRUSTED_DRAM_ID
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else ifeq (${FVP_TSP_RAM_LOCATION}, dram)
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FVP_TSP_RAM_LOCATION_ID := FVP_DRAM_ID
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else
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$(error "Unsupported FVP_TSP_RAM_LOCATION value")
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endif
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