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AArch32: Add support for ARM Cortex-A32 MPCore Processor
This patch adds ARM Cortex-A32 MPCore Processor support in the CPU specific operations framework. It also includes this support for the Base FVP port. Change-Id: If3697b88678df737c29f79cf3fa1ea2cb6fa565d
This commit is contained in:
Yatharth Kochar
parent
d991551872
commit
03a3042b04
3 changed files with 188 additions and 0 deletions
44
include/lib/cpus/aarch32/cortex_a32.h
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include/lib/cpus/aarch32/cortex_a32.h
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __CORTEX_A32_H__
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#define __CORTEX_A32_H__
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/* Cortex-A32 Main ID register for revision 0 */
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#define CORTEX_A32_MIDR 0x410FD010
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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* CPUECTLR_EL1 is an implementation-specific register.
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******************************************************************************/
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#define CORTEX_A32_CPUECTLR_EL1 p15, 1, c15
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#define CORTEX_A32_CPUECTLR_SMPEN_BIT (1 << 6)
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#endif /* __CORTEX_A32_H__ */
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142
lib/cpus/aarch32/cortex_a32.S
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lib/cpus/aarch32/cortex_a32.S
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@ -0,0 +1,142 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <cortex_a32.h>
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#include <cpu_macros.S>
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/* ---------------------------------------------
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* Disable intra-cluster coherency
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* Clobbers: r0-r1
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* ---------------------------------------------
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*/
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func cortex_a32_disable_smp
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ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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bic r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
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stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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isb
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dsb sy
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bx lr
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endfunc cortex_a32_disable_smp
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A32.
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* Clobbers: r0-r1
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* -------------------------------------------------
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*/
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func cortex_a32_reset_func
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/* ---------------------------------------------
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* Enable the SMP bit.
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* ---------------------------------------------
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*/
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ldcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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orr r0, r0, #CORTEX_A32_CPUECTLR_SMPEN_BIT
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stcopr16 r0, r1, CORTEX_A32_CPUECTLR_EL1
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isb
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bx lr
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endfunc cortex_a32_reset_func
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/* ----------------------------------------------------
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* The CPU Ops core power down function for Cortex-A32.
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* Clobbers: r0-r3
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* ----------------------------------------------------
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*/
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func cortex_a32_core_pwr_dwn
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push {lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 caches.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {lr}
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b cortex_a32_disable_smp
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endfunc cortex_a32_core_pwr_dwn
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/* -------------------------------------------------------
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* The CPU Ops cluster power down function for Cortex-A32.
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* Clobbers: r0-r3
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* -------------------------------------------------------
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*/
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func cortex_a32_cluster_pwr_dwn
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push {lr}
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/* Assert if cache is enabled */
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#if ASM_ASSERTION
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ldcopr r0, SCTLR
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tst r0, #SCTLR_C_BIT
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ASM_ASSERT(eq)
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#endif
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/* ---------------------------------------------
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* Flush L1 cache.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level1
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/* ---------------------------------------------
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* Disable the optional ACP.
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* ---------------------------------------------
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*/
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bl plat_disable_acp
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/* ---------------------------------------------
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* Flush L2 cache.
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* ---------------------------------------------
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*/
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mov r0, #DC_OP_CISW
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bl dcsw_op_level2
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/* ---------------------------------------------
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* Come out of intra cluster coherency
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* ---------------------------------------------
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*/
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pop {lr}
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b cortex_a32_disable_smp
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endfunc cortex_a32_cluster_pwr_dwn
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declare_cpu_ops cortex_a32, CORTEX_A32_MIDR
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@ -109,6 +109,8 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a57.S \
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lib/cpus/aarch64/cortex_a72.S \
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lib/cpus/aarch64/cortex_a73.S
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else
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FVP_CPU_LIBS += lib/cpus/aarch32/cortex_a32.S
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endif
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BL1_SOURCES += drivers/io/io_semihosting.c \
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