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build(corstone1000): rename diphda to corstone1000

Browse source 
diphda platform is now being renamed to corstone1000.
These changes are to replace all the instances and traces
of diphda  corstone1000.

Change-Id: I330f3a112d232b99b4721b6bf0236253b068dbba
Signed-off-by: Arpita S.K <Arpita.S.K@arm.com>
Signed-off-by: Vishnu Banavath <vishnu.banavath@arm.com>
This commit is contained in:
Vishnu Banavath 2022-01-19 18:43:12 +00:00 • committed by Emekcan Aras
parent b22f18e365
commit 0260eb0d15
19 changed files with 145 additions and 145 deletions
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2
docs/about/maintainers.rst
View file

@ -427,7 +427,7 @@ Arm Rich IoT Platform ports
:|G|: `vishnu-banavath`_ :|G|: `vishnu-banavath`_
:|F|: plat/arm/board/corstone700 :|F|: plat/arm/board/corstone700
:|F|: plat/arm/board/a5ds :|F|: plat/arm/board/a5ds
:|F|: plat/arm/board/diphda :|F|: plat/arm/board/corstone1000
Arm Reference Design platform ports Arm Reference Design platform ports
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

6
docs/plat/arm/diphda/index.rst → docs/plat/arm/corstone1000/index.rst
View file

@ -1,7 +1,7 @@
Diphda Platform Corstone1000 Platform
========================== ==========================
Some of the features of the Diphda platform referenced in TF-A include: Some of the features of the Corstone1000 platform referenced in TF-A include:
- Cortex-A35 application processor (64-bit mode) - Cortex-A35 application processor (64-bit mode)
- Secure Enclave - Secure Enclave
@ -37,7 +37,7 @@ Build Procedure (TF-A only)
CC=aarch64-none-elf-gcc \ CC=aarch64-none-elf-gcc \
V=1 \ V=1 \
BUILD_BASE=<path to the build folder> \ BUILD_BASE=<path to the build folder> \
PLAT=diphda \ PLAT=corstone1000 \
SPD=spmd \ SPD=spmd \
SPMD_SPM_AT_SEL2=0 \ SPMD_SPM_AT_SEL2=0 \
DEBUG=1 \ DEBUG=1 \

2
docs/plat/arm/index.rst
View file

@ -13,7 +13,7 @@ Arm Development Platforms
arm_fpga/index arm_fpga/index
arm-build-options arm-build-options
morello/index morello/index
diphda/index corstone1000/index
This chapter holds documentation related to Arm's development platforms, This chapter holds documentation related to Arm's development platforms,
including both software models (FVPs) and hardware development boards including both software models (FVPs) and hardware development boards

4
plat/arm/board/common/rotpk/arm_dev_rotpk.S
View file

@ -1,10 +1,10 @@
/* /*
* Copyright (c) 2021, ARM Limited. All rights reserved. * Copyright (c) 2021-2022, ARM Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
/* diphda platform provides custom values for the macros defined in /* corstone1000 platform provides custom values for the macros defined in
* arm_def.h , so only platform_def.h needs to be included * arm_def.h , so only platform_def.h needs to be included
*/ */
#if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA) #if !defined(TARGET_PLATFORM_FVP) && !defined(TARGET_PLATFORM_FPGA)

10
plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c → plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -44,7 +44,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP, SET_STATIC_PARAM_HEAD(ep_info, PARAM_EP,
VERSION_2, entry_point_info_t, SECURE | EXECUTABLE), VERSION_2, entry_point_info_t, SECURE | EXECUTABLE),
.ep_info.pc = BL32_BASE, .ep_info.pc = BL32_BASE,
.ep_info.args.arg0 = DIPHDA_TOS_FW_CONFIG_BASE, .ep_info.args.arg0 = CORSTONE1000_TOS_FW_CONFIG_BASE,
SET_STATIC_PARAM_HEAD(image_info, PARAM_EP, SET_STATIC_PARAM_HEAD(image_info, PARAM_EP,
VERSION_2, image_info_t, 0), VERSION_2, image_info_t, 0),
.image_info.image_base = BL32_BASE, .image_info.image_base = BL32_BASE,
@ -56,9 +56,9 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
/* Fill TOS_FW_CONFIG related information */ /* Fill TOS_FW_CONFIG related information */
{ {
.image_id = TOS_FW_CONFIG_ID, .image_id = TOS_FW_CONFIG_ID,
.image_info.image_base = DIPHDA_TOS_FW_CONFIG_BASE, .image_info.image_base = CORSTONE1000_TOS_FW_CONFIG_BASE,
.image_info.image_max_size = DIPHDA_TOS_FW_CONFIG_LIMIT - \ .image_info.image_max_size = CORSTONE1000_TOS_FW_CONFIG_LIMIT - \
DIPHDA_TOS_FW_CONFIG_BASE, CORSTONE1000_TOS_FW_CONFIG_BASE,
SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY, SET_STATIC_PARAM_HEAD(ep_info, PARAM_IMAGE_BINARY,
VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE), VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY, SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,

4
plat/arm/board/diphda/common/diphda_err.c → plat/arm/board/corstone1000/common/corstone1000_err.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,7 +7,7 @@
#include <plat/arm/common/plat_arm.h> #include <plat/arm/common/plat_arm.h>
/* /*
* diphda error handler * corstone1000 error handler
*/ */
void __dead2 plat_arm_error_handler(int err) void __dead2 plat_arm_error_handler(int err)
{ {

6
plat/arm/board/diphda/common/diphda_helpers.S → plat/arm/board/corstone1000/common/corstone1000_helpers.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -29,7 +29,7 @@ endfunc plat_secondary_cold_boot_setup
* unsigned long plat_get_my_entrypoint (void); * unsigned long plat_get_my_entrypoint (void);
* *
* Main job of this routine is to distinguish between a cold and warm * Main job of this routine is to distinguish between a cold and warm
* boot. On diphda, this information can be queried from the power * boot. On corstone1000, this information can be queried from the power
* controller. The Power Control SYS Status Register (PSYSR) indicates * controller. The Power Control SYS Status Register (PSYSR) indicates
* the wake-up reason for the CPU. * the wake-up reason for the CPU.
* *
@ -61,7 +61,7 @@ func plat_is_my_cpu_primary
mrs x0, mpidr_el1 mrs x0, mpidr_el1
mov_imm x1, MPIDR_AFFINITY_MASK mov_imm x1, MPIDR_AFFINITY_MASK
and x0, x0, x1 and x0, x0, x1
cmp x0, #DIPHDA_PRIMARY_CPU cmp x0, #CORSTONE1000_PRIMARY_CPU
cset w0, eq cset w0, eq
ret ret
endfunc plat_is_my_cpu_primary endfunc plat_is_my_cpu_primary

8
plat/arm/board/diphda/common/diphda_plat.c → plat/arm/board/corstone1000/common/corstone1000_plat.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -21,12 +21,12 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM, ARM_MAP_SHARED_RAM,
ARM_MAP_NS_SHARED_RAM, ARM_MAP_NS_SHARED_RAM,
ARM_MAP_NS_DRAM1, ARM_MAP_NS_DRAM1,
DIPHDA_MAP_DEVICE, CORSTONE1000_MAP_DEVICE,
DIPHDA_EXTERNAL_FLASH, CORSTONE1000_EXTERNAL_FLASH,
{0} {0}
}; };
/* diphda only has one always-on power domain and there /* corstone1000 only has one always-on power domain and there
* is no power control present * is no power control present
*/ */
void __init plat_arm_pwrc_setup(void) void __init plat_arm_pwrc_setup(void)

0
plat/arm/board/diphda/common/diphda_pm.c → plat/arm/board/corstone1000/common/corstone1000_pm.c
View file

2
plat/arm/board/diphda/common/diphda_security.c → plat/arm/board/corstone1000/common/corstone1000_security.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */

2
plat/arm/board/diphda/common/diphda_stack_protector.c → plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */

14
plat/arm/board/diphda/common/diphda_topology.c → plat/arm/board/corstone1000/common/corstone1000_topology.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -7,8 +7,8 @@
#include <plat/arm/common/plat_arm.h> #include <plat/arm/common/plat_arm.h>
#include <plat/common/platform.h> #include <plat/common/platform.h>
/* The diphda power domain tree descriptor */ /* The corstone1000 power domain tree descriptor */
static unsigned char diphda_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT static unsigned char corstone1000_power_domain_tree_desc[PLAT_ARM_CLUSTER_COUNT
+ 2]; + 2];
/******************************************************************************* /*******************************************************************************
* This function dynamically constructs the topology according to * This function dynamically constructs the topology according to
@ -22,13 +22,13 @@ const unsigned char *plat_get_power_domain_tree_desc(void)
* The highest level is the system level. The next level is constituted * The highest level is the system level. The next level is constituted
* by clusters and then cores in clusters. * by clusters and then cores in clusters.
*/ */
diphda_power_domain_tree_desc[0] = 1; corstone1000_power_domain_tree_desc[0] = 1;
diphda_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT; corstone1000_power_domain_tree_desc[1] = PLAT_ARM_CLUSTER_COUNT;
for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++) for (i = 0; i < PLAT_ARM_CLUSTER_COUNT; i++)
diphda_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT; corstone1000_power_domain_tree_desc[i + 2] = PLATFORM_CORE_COUNT;
return diphda_power_domain_tree_desc; return corstone1000_power_domain_tree_desc;
} }
/****************************************************************************** /******************************************************************************

4
plat/arm/board/diphda/common/diphda_trusted_boot.c → plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -38,7 +38,7 @@ int plat_get_rotpk_info(void *cookie, void **key_ptr, unsigned int *key_len,
*/ */
int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr) int plat_get_nv_ctr(void *cookie, unsigned int *nv_ctr)
{ {
*nv_ctr = DIPHDA_FW_NVCTR_VAL; *nv_ctr = CORSTONE1000_FW_NVCTR_VAL;
return 0; return 0;
} }

2
plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts → plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited. All rights reserved. * Copyright (c) 2021-2022, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */

54
plat/arm/board/diphda/common/include/platform_def.h → plat/arm/board/corstone1000/common/include/platform_def.h
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, Arm Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */
@ -34,17 +34,17 @@
#define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000 #define V2M_IOFPGA_UART0_CLK_IN_HZ 50000000
#define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000 #define V2M_IOFPGA_UART1_CLK_IN_HZ 50000000
/* Core/Cluster/Thread counts for diphda */ /* Core/Cluster/Thread counts for corstone1000 */
#define DIPHDA_CLUSTER_COUNT U(1) #define CORSTONE1000_CLUSTER_COUNT U(1)
#define DIPHDA_MAX_CPUS_PER_CLUSTER U(4) #define CORSTONE1000_MAX_CPUS_PER_CLUSTER U(4)
#define DIPHDA_MAX_PE_PER_CPU U(1) #define CORSTONE1000_MAX_PE_PER_CPU U(1)
#define DIPHDA_PRIMARY_CPU U(0) #define CORSTONE1000_PRIMARY_CPU U(0)
#define PLAT_ARM_CLUSTER_COUNT DIPHDA_CLUSTER_COUNT #define PLAT_ARM_CLUSTER_COUNT CORSTONE1000_CLUSTER_COUNT
#define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \ #define PLATFORM_CORE_COUNT (PLAT_ARM_CLUSTER_COUNT * \
DIPHDA_MAX_CPUS_PER_CLUSTER * \ CORSTONE1000_MAX_CPUS_PER_CLUSTER * \
DIPHDA_MAX_PE_PER_CPU) CORSTONE1000_MAX_PE_PER_CPU)
/* UART related constants */ /* UART related constants */
#define PLAT_ARM_BOOT_UART_BASE 0x1a510000 #define PLAT_ARM_BOOT_UART_BASE 0x1a510000
@ -85,7 +85,7 @@
* *
* BL32 (optee-os) * BL32 (optee-os)
* *
* <DIPHDA_TOS_FW_CONFIG_BASE> = 0x20ae000 * <CORSTONE1000_TOS_FW_CONFIG_BASE> = 0x20ae000
* *
* partition size: 8 KB * partition size: 8 KB
* *
@ -132,7 +132,7 @@
#define ARM_DRAM1_END (ARM_DRAM1_BASE + \ #define ARM_DRAM1_END (ARM_DRAM1_BASE + \
ARM_DRAM1_SIZE - 1) ARM_DRAM1_SIZE - 1)
/* DRAM1 and DRAM2 are the same for diphda */ /* DRAM1 and DRAM2 are the same for corstone1000 */
#define ARM_DRAM2_BASE ARM_DRAM1_BASE #define ARM_DRAM2_BASE ARM_DRAM1_BASE
#define ARM_DRAM2_SIZE ARM_DRAM1_SIZE #define ARM_DRAM2_SIZE ARM_DRAM1_SIZE
#define ARM_DRAM2_END ARM_DRAM1_END #define ARM_DRAM2_END ARM_DRAM1_END
@ -173,13 +173,13 @@
PLAT_ARM_MAX_BL31_SIZE) PLAT_ARM_MAX_BL31_SIZE)
#define BL31_LIMIT BL2_SIGNATURE_BASE #define BL31_LIMIT BL2_SIGNATURE_BASE
#define DIPHDA_TOS_FW_CONFIG_BASE (BL31_BASE - \ #define CORSTONE1000_TOS_FW_CONFIG_BASE (BL31_BASE - \
DIPHDA_TOS_FW_CONFIG_SIZE) CORSTONE1000_TOS_FW_CONFIG_SIZE)
#define DIPHDA_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */ #define CORSTONE1000_TOS_FW_CONFIG_SIZE UL(0x00002000) /* 8 KB */
#define DIPHDA_TOS_FW_CONFIG_LIMIT BL31_BASE #define CORSTONE1000_TOS_FW_CONFIG_LIMIT BL31_BASE
#define BL32_BASE ARM_BL_RAM_BASE #define BL32_BASE ARM_BL_RAM_BASE
#define PLAT_ARM_MAX_BL32_SIZE (DIPHDA_TOS_FW_CONFIG_BASE - \ #define PLAT_ARM_MAX_BL32_SIZE (CORSTONE1000_TOS_FW_CONFIG_BASE - \
BL32_BASE) /* 688 KB */ BL32_BASE) /* 688 KB */
#define BL32_LIMIT (BL32_BASE + \ #define BL32_LIMIT (BL32_BASE + \
PLAT_ARM_MAX_BL32_SIZE) PLAT_ARM_MAX_BL32_SIZE)
@ -220,7 +220,7 @@
/* /*
* Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo. * Define FW_CONFIG area base and limit. Leave enough space for BL2 meminfo.
* FW_CONFIG is intended to host the device tree. Currently, This area is not * FW_CONFIG is intended to host the device tree. Currently, This area is not
* used because diphda platform doesn't use a device tree at TF-A level. * used because corstone1000 platform doesn't use a device tree at TF-A level.
*/ */
#define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \ #define ARM_FW_CONFIG_BASE (ARM_SHARED_RAM_BASE \
+ sizeof(meminfo_t)) + sizeof(meminfo_t))
@ -261,8 +261,8 @@
#define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */ #define SYS_COUNTER_FREQ_IN_TICKS UL(50000000) /* 50MHz */
#define DIPHDA_IRQ_TZ_WDOG 32 #define CORSTONE1000_IRQ_TZ_WDOG 32
#define DIPHDA_IRQ_SEC_SYS_TIMER 34 #define CORSTONE1000_IRQ_SEC_SYS_TIMER 34
#define PLAT_MAX_PWR_LVL 2 #define PLAT_MAX_PWR_LVL 2
/* /*
@ -308,7 +308,7 @@
#define PLATFORM_STACK_SIZE UL(0x440) #define PLATFORM_STACK_SIZE UL(0x440)
#define DIPHDA_EXTERNAL_FLASH MAP_REGION_FLAT( \ #define CORSTONE1000_EXTERNAL_FLASH MAP_REGION_FLAT( \
PLAT_ARM_NVM_BASE, \ PLAT_ARM_NVM_BASE, \
PLAT_ARM_NVM_SIZE, \ PLAT_ARM_NVM_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE) MT_DEVICE | MT_RO | MT_SECURE)
@ -356,11 +356,11 @@
ARM_FW_CONFIG_BASE), \ ARM_FW_CONFIG_BASE), \
MT_MEMORY | MT_RW | MT_SECURE) MT_MEMORY | MT_RW | MT_SECURE)
#define DIPHDA_DEVICE_BASE (0x1A000000) #define CORSTONE1000_DEVICE_BASE (0x1A000000)
#define DIPHDA_DEVICE_SIZE (0x26000000) #define CORSTONE1000_DEVICE_SIZE (0x26000000)
#define DIPHDA_MAP_DEVICE MAP_REGION_FLAT( \ #define CORSTONE1000_MAP_DEVICE MAP_REGION_FLAT( \
DIPHDA_DEVICE_BASE, \ CORSTONE1000_DEVICE_BASE, \
DIPHDA_DEVICE_SIZE, \ CORSTONE1000_DEVICE_SIZE, \
MT_DEVICE | MT_RW | MT_SECURE) MT_DEVICE | MT_RW | MT_SECURE)
#define ARM_IRQ_SEC_PHY_TIMER 29 #define ARM_IRQ_SEC_PHY_TIMER 29
@ -406,9 +406,9 @@
*/ */
#define PLAT_ARM_G1S_IRQ_PROPS(grp) \ #define PLAT_ARM_G1S_IRQ_PROPS(grp) \
ARM_G1S_IRQ_PROPS(grp), \ ARM_G1S_IRQ_PROPS(grp), \
INTR_PROP_DESC(DIPHDA_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \ INTR_PROP_DESC(CORSTONE1000_IRQ_TZ_WDOG, GIC_HIGHEST_SEC_PRIORITY, \
(grp), GIC_INTR_CFG_LEVEL), \ (grp), GIC_INTR_CFG_LEVEL), \
INTR_PROP_DESC(DIPHDA_IRQ_SEC_SYS_TIMER, \ INTR_PROP_DESC(CORSTONE1000_IRQ_SEC_SYS_TIMER, \
GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL) GIC_HIGHEST_SEC_PRIORITY, (grp), GIC_INTR_CFG_LEVEL)
#define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp) #define PLAT_ARM_G0_IRQ_PROPS(grp) ARM_G0_IRQ_PROPS(grp)

2
plat/arm/board/diphda/include/plat_macros.S → plat/arm/board/corstone1000/include/plat_macros.S
View file

@ -1,5 +1,5 @@
/* /*
* Copyright (c) 2021, ARM Limited and Contributors. All rights reserved. * Copyright (c) 2021-2022, ARM Limited and Contributors. All rights reserved.
* *
* SPDX-License-Identifier: BSD-3-Clause * SPDX-License-Identifier: BSD-3-Clause
*/ */

83
plat/arm/board/corstone1000/platform.mk Normal file
View file

@ -0,0 +1,83 @@
#
# Copyright (c) 2021-2022, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Making sure the corstone1000 platform type is specified
ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
$(error TARGET_PLATFORM must be fpga or fvp)
endif
CORSTONE1000_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S
PLAT_INCLUDES := -Iplat/arm/board/corstone1000/common/include \
-Iplat/arm/board/corstone1000/include \
-Iinclude/plat/arm/common \
-Iinclude/plat/arm/css/common/aarch64
CORSTONE1000_FW_NVCTR_VAL := 255
TFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL}
NTFW_NVCTR_VAL := ${CORSTONE1000_FW_NVCTR_VAL}
override NEED_BL1 := no
override NEED_BL2 := yes
FIP_BL2_ARGS := tb-fw
override NEED_BL2U := no
override NEED_BL31 := yes
NEED_BL32 := yes
override NEED_BL33 := yes
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
CORSTONE1000_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
BL2_SOURCES += plat/arm/board/corstone1000/common/corstone1000_security.c \
plat/arm/board/corstone1000/common/corstone1000_err.c \
plat/arm/board/corstone1000/common/corstone1000_trusted_boot.c \
lib/utils/mem_region.c \
plat/arm/board/corstone1000/common/corstone1000_helpers.S \
plat/arm/board/corstone1000/common/corstone1000_plat.c \
plat/arm/board/corstone1000/common/corstone1000_bl2_mem_params_desc.c \
${CORSTONE1000_CPU_LIBS} \
BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/board/corstone1000/common/corstone1000_helpers.S \
plat/arm/board/corstone1000/common/corstone1000_topology.c \
plat/arm/board/corstone1000/common/corstone1000_security.c \
plat/arm/board/corstone1000/common/corstone1000_plat.c \
plat/arm/board/corstone1000/common/corstone1000_pm.c \
${CORSTONE1000_CPU_LIBS} \
${CORSTONE1000_GIC_SOURCES}
ifneq (${ENABLE_STACK_PROTECTOR},0)
ifneq (${ENABLE_STACK_PROTECTOR},none)
CORSTONE1000_SECURITY_SOURCES := plat/arm/board/corstone1000/common/corstone1000_stack_protector.c
BL2_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
BL31_SOURCES += ${CORSTONE1000_SECURITY_SOURCES}
endif
endif
FDT_SOURCES += plat/arm/board/corstone1000/common/fdts/corstone1000_spmc_manifest.dts
CORSTONE1000_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/corstone1000_spmc_manifest.dtb
# Add the SPMC manifest to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${CORSTONE1000_TOS_FW_CONFIG},--tos-fw-config,${CORSTONE1000_TOS_FW_CONFIG}))
# Adding TARGET_PLATFORM as a GCC define (-D option)
$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
# Adding CORSTONE1000_FW_NVCTR_VAL as a GCC define (-D option)
$(eval $(call add_define,CORSTONE1000_FW_NVCTR_VAL))
include plat/arm/common/arm_common.mk
include plat/arm/board/common/board_common.mk

83
plat/arm/board/diphda/platform.mk
View file

@ -1,83 +0,0 @@
#
# Copyright (c) 2021, Arm Limited and Contributors. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
# Making sure the diphda platform type is specified
ifeq ($(filter ${TARGET_PLATFORM}, fpga fvp),)
$(error TARGET_PLATFORM must be fpga or fvp)
endif
DIPHDA_CPU_LIBS +=lib/cpus/aarch64/cortex_a35.S
PLAT_INCLUDES := -Iplat/arm/board/diphda/common/include \
-Iplat/arm/board/diphda/include \
-Iinclude/plat/arm/common \
-Iinclude/plat/arm/css/common/aarch64
DIPHDA_FW_NVCTR_VAL := 255
TFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL}
NTFW_NVCTR_VAL := ${DIPHDA_FW_NVCTR_VAL}
override NEED_BL1 := no
override NEED_BL2 := yes
FIP_BL2_ARGS := tb-fw
override NEED_BL2U := no
override NEED_BL31 := yes
NEED_BL32 := yes
override NEED_BL33 := yes
# Include GICv2 driver files
include drivers/arm/gic/v2/gicv2.mk
DIPHDA_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c \
plat/arm/common/arm_gicv2.c
BL2_SOURCES += plat/arm/board/diphda/common/diphda_security.c \
plat/arm/board/diphda/common/diphda_err.c \
plat/arm/board/diphda/common/diphda_trusted_boot.c \
lib/utils/mem_region.c \
plat/arm/board/diphda/common/diphda_helpers.S \
plat/arm/board/diphda/common/diphda_plat.c \
plat/arm/board/diphda/common/diphda_bl2_mem_params_desc.c \
${DIPHDA_CPU_LIBS} \
BL31_SOURCES += drivers/cfi/v2m/v2m_flash.c \
lib/utils/mem_region.c \
plat/arm/board/diphda/common/diphda_helpers.S \
plat/arm/board/diphda/common/diphda_topology.c \
plat/arm/board/diphda/common/diphda_security.c \
plat/arm/board/diphda/common/diphda_plat.c \
plat/arm/board/diphda/common/diphda_pm.c \
${DIPHDA_CPU_LIBS} \
${DIPHDA_GIC_SOURCES}
ifneq (${ENABLE_STACK_PROTECTOR},0)
ifneq (${ENABLE_STACK_PROTECTOR},none)
DIPHDA_SECURITY_SOURCES := plat/arm/board/diphda/common/diphda_stack_protector.c
BL2_SOURCES += ${DIPHDA_SECURITY_SOURCES}
BL31_SOURCES += ${DIPHDA_SECURITY_SOURCES}
endif
endif
FDT_SOURCES += plat/arm/board/diphda/common/fdts/diphda_spmc_manifest.dts
DIPHDA_TOS_FW_CONFIG := ${BUILD_PLAT}/fdts/diphda_spmc_manifest.dtb
# Add the SPMC manifest to FIP and specify the same to certtool
$(eval $(call TOOL_ADD_PAYLOAD,${DIPHDA_TOS_FW_CONFIG},--tos-fw-config,${DIPHDA_TOS_FW_CONFIG}))
# Adding TARGET_PLATFORM as a GCC define (-D option)
$(eval $(call add_define,TARGET_PLATFORM_$(call uppercase,${TARGET_PLATFORM})))
# Adding DIPHDA_FW_NVCTR_VAL as a GCC define (-D option)
$(eval $(call add_define,DIPHDA_FW_NVCTR_VAL))
include plat/arm/common/arm_common.mk
include plat/arm/board/common/board_common.mk

2
plat/arm/common/arm_common.mk
View file

@ -282,7 +282,7 @@ endif
ifeq (${JUNO_AARCH32_EL3_RUNTIME},1) ifeq (${JUNO_AARCH32_EL3_RUNTIME},1)
BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c BL2_SOURCES += plat/arm/common/aarch32/arm_bl2_mem_params_desc.c
else else
ifneq (${PLAT}, diphda) ifneq (${PLAT}, corstone1000)
BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c BL2_SOURCES += plat/arm/common/${ARCH}/arm_bl2_mem_params_desc.c
endif endif
endif endif