From 0147bef523e27e26c0240fef4b47deca6720566c Mon Sep 17 00:00:00 2001 From: Etienne Carriere Date: Sun, 5 Nov 2017 22:55:47 +0100 Subject: [PATCH] ARMv7 does not support STL instruction Also need to add a SEV instruction in ARMv7 spin_unlock which is implicit in ARMv8. Signed-off-by: Etienne Carriere --- include/common/aarch32/asm_macros.S | 9 +++++++++ lib/locks/exclusive/aarch32/spinlock.S | 12 ++++++++++++ 2 files changed, 21 insertions(+) diff --git a/include/common/aarch32/asm_macros.S b/include/common/aarch32/asm_macros.S index f5737449e..0d1a37d1e 100644 --- a/include/common/aarch32/asm_macros.S +++ b/include/common/aarch32/asm_macros.S @@ -79,6 +79,15 @@ ldr r0, =(\_name + \_size) .endm +#if (ARM_ARCH_MAJOR == 7) + /* ARMv7 does not support stl instruction */ + .macro stl _reg, _write_lock + dmb + str \_reg, \_write_lock + dsb + .endm +#endif + /* * Helper macro to generate the best mov/movw/movt combinations * according to the value to be moved. diff --git a/lib/locks/exclusive/aarch32/spinlock.S b/lib/locks/exclusive/aarch32/spinlock.S index bc77bc9c4..9492cc081 100644 --- a/lib/locks/exclusive/aarch32/spinlock.S +++ b/lib/locks/exclusive/aarch32/spinlock.S @@ -9,6 +9,17 @@ .globl spin_lock .globl spin_unlock +#if ARM_ARCH_AT_LEAST(8, 0) +/* + * According to the ARMv8-A Architecture Reference Manual, "when the global + * monitor for a PE changes from Exclusive Access state to Open Access state, + * an event is generated.". This applies to both AArch32 and AArch64 modes of + * ARMv8-A. As a result, no explicit SEV with unlock is required. + */ +#define COND_SEV() +#else +#define COND_SEV() sev +#endif func spin_lock mov r2, #1 @@ -27,5 +38,6 @@ endfunc spin_lock func spin_unlock mov r1, #0 stl r1, [r0] + COND_SEV() bx lr endfunc spin_unlock