diff --git a/Makefile b/Makefile index 98f47a71d..3ec41518a 100644 --- a/Makefile +++ b/Makefile @@ -710,16 +710,23 @@ endif BL32_LDFLAGS += $(PIE_LDFLAGS) endif -ifeq (${ARCH},aarch64) +BL1_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} +BL31_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} +BL32_CPPFLAGS += -DREPORT_ERRATA=${DEBUG} + BL1_CPPFLAGS += -DIMAGE_AT_EL3 ifeq ($(RESET_TO_BL2),1) BL2_CPPFLAGS += -DIMAGE_AT_EL3 else BL2_CPPFLAGS += -DIMAGE_AT_EL1 endif + +ifeq (${ARCH},aarch64) BL2U_CPPFLAGS += -DIMAGE_AT_EL1 BL31_CPPFLAGS += -DIMAGE_AT_EL3 BL32_CPPFLAGS += -DIMAGE_AT_EL1 +else +BL32_CPPFLAGS += -DIMAGE_AT_EL3 endif # Include the CPU specific operations makefile, which provides default diff --git a/drivers/st/crypto/stm32_pka.c b/drivers/st/crypto/stm32_pka.c index 1e7c42c95..9124cf2cb 100644 --- a/drivers/st/crypto/stm32_pka.c +++ b/drivers/st/crypto/stm32_pka.c @@ -33,10 +33,10 @@ #define UINT8_LEN 8U #define UINT64_LEN (UINT8_LEN * sizeof(uint64_t)) -#define WORD_SIZE (sizeof(uint64_t)) +#define PKA_WORD_SIZE (sizeof(uint64_t)) #define OP_NBW_FROM_LEN(len) (DIV_ROUND_UP_2EVAL((len), UINT64_LEN) + 1) #define OP_NBW_FROM_SIZE(s) OP_NBW_FROM_LEN((s) * UINT8_LEN) -#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * WORD_SIZE) +#define OP_SIZE_FROM_SIZE(s) (OP_NBW_FROM_SIZE(s) * PKA_WORD_SIZE) #define DT_PKA_COMPAT "st,stm32-pka64" diff --git a/include/arch/aarch32/asm_macros.S b/include/arch/aarch32/asm_macros.S index 483f9fe05..83e94caa4 100644 --- a/include/arch/aarch32/asm_macros.S +++ b/include/arch/aarch32/asm_macros.S @@ -1,5 +1,5 @@ /* - * Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2016-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ @@ -8,6 +8,7 @@ #include #include +#include #include /* @@ -24,8 +25,6 @@ stcopr _reg, _coproc #endif -#define WORD_SIZE 4 - /* * Co processor register accessors */ @@ -49,14 +48,14 @@ .macro dcache_line_size reg, tmp ldcopr \tmp, CTR ubfx \tmp, \tmp, #CTR_DMINLINE_SHIFT, #CTR_DMINLINE_WIDTH - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm .macro icache_line_size reg, tmp ldcopr \tmp, CTR and \tmp, \tmp, #CTR_IMINLINE_MASK - mov \reg, #WORD_SIZE + mov \reg, #CPU_WORD_SIZE lsl \reg, \reg, \tmp .endm diff --git a/include/lib/cpus/aarch32/cpu_macros.S b/include/lib/cpus/aarch32/cpu_macros.S index ab2f2c62a..02999ae6c 100644 --- a/include/lib/cpus/aarch32/cpu_macros.S +++ b/include/lib/cpus/aarch32/cpu_macros.S @@ -7,77 +7,9 @@ #define CPU_MACROS_S #include +#include #include -#if defined(IMAGE_BL1) || defined(IMAGE_BL32) \ - || (defined(IMAGE_BL2) && RESET_TO_BL2) -#define IMAGE_AT_EL3 -#endif - -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -/* Word size for 32-bit CPUs */ -#define CPU_WORD_SIZE 4 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL32 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL32)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL32 */ -#ifndef IMAGE_BL32 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL32 requires mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL32)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based on the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_PWR_DWN_OPS, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_OPS_SIZE, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE - /* * Write given expressions as words * diff --git a/include/lib/cpus/aarch64/cpu_macros.S b/include/lib/cpus/aarch64/cpu_macros.S index 041be5153..6fecb40f4 100644 --- a/include/lib/cpus/aarch64/cpu_macros.S +++ b/include/lib/cpus/aarch64/cpu_macros.S @@ -1,96 +1,15 @@ /* - * Copyright (c) 2014-2022, ARM Limited and Contributors. All rights reserved. + * Copyright (c) 2014-2023, ARM Limited and Contributors. All rights reserved. * * SPDX-License-Identifier: BSD-3-Clause */ #ifndef CPU_MACROS_S #define CPU_MACROS_S -#include #include +#include #include -#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ - (MIDR_PN_MASK << MIDR_PN_SHIFT) - -/* The number of CPU operations allowed */ -#define CPU_MAX_PWR_DWN_OPS 2 - -/* Special constant to specify that CPU has no reset function */ -#define CPU_NO_RESET_FUNC 0 - -#define CPU_NO_EXTRA1_FUNC 0 -#define CPU_NO_EXTRA2_FUNC 0 -#define CPU_NO_EXTRA3_FUNC 0 - -/* Word size for 64-bit CPUs */ -#define CPU_WORD_SIZE 8 - -/* - * Whether errata status needs reporting. Errata status is printed in debug - * builds for both BL1 and BL31 images. - */ -#if (defined(IMAGE_BL1) || defined(IMAGE_BL31)) && DEBUG -# define REPORT_ERRATA 1 -#else -# define REPORT_ERRATA 0 -#endif - - - .equ CPU_MIDR_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA1_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA2_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_EXTRA3_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_E_HANDLER_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_RESET_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_PWR_DWN_OPS_SIZE, CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS - .equ CPU_ERRATA_FUNC_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_LOCK_SIZE, CPU_WORD_SIZE - .equ CPU_ERRATA_PRINTED_SIZE, CPU_WORD_SIZE - .equ CPU_REG_DUMP_SIZE, CPU_WORD_SIZE - -#ifndef IMAGE_AT_EL3 - .equ CPU_RESET_FUNC_SIZE, 0 -#endif - -/* The power down core and cluster is needed only in BL31 */ -#ifndef IMAGE_BL31 - .equ CPU_PWR_DWN_OPS_SIZE, 0 -#endif - -/* Fields required to print errata status. */ -#if !REPORT_ERRATA - .equ CPU_ERRATA_FUNC_SIZE, 0 -#endif - -/* Only BL31 requieres mutual exclusion and printed flag. */ -#if !(REPORT_ERRATA && defined(IMAGE_BL31)) - .equ CPU_ERRATA_LOCK_SIZE, 0 - .equ CPU_ERRATA_PRINTED_SIZE, 0 -#endif - -#if !defined(IMAGE_BL31) || !CRASH_REPORTING - .equ CPU_REG_DUMP_SIZE, 0 -#endif - -/* - * Define the offsets to the fields in cpu_ops structure. - * Every offset is defined based in the offset and size of the previous - * field. - */ - .equ CPU_MIDR, 0 - .equ CPU_RESET_FUNC, CPU_MIDR + CPU_MIDR_SIZE - .equ CPU_EXTRA1_FUNC, CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE - .equ CPU_EXTRA2_FUNC, CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE - .equ CPU_EXTRA3_FUNC, CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE - .equ CPU_E_HANDLER_FUNC, CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE - .equ CPU_PWR_DWN_OPS, CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE - .equ CPU_ERRATA_FUNC, CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE - .equ CPU_ERRATA_LOCK, CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE - .equ CPU_ERRATA_PRINTED, CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE - .equ CPU_REG_DUMP, CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE - .equ CPU_OPS_SIZE, CPU_REG_DUMP + CPU_REG_DUMP_SIZE - /* * Write given expressions as quad words * diff --git a/include/lib/cpus/cpu_ops.h b/include/lib/cpus/cpu_ops.h new file mode 100644 index 000000000..0854fec00 --- /dev/null +++ b/include/lib/cpus/cpu_ops.h @@ -0,0 +1,105 @@ +/* + * Copyright (c) 2023, ARM Limited and Contributors. All rights reserved. + * + * SPDX-License-Identifier: BSD-3-Clause + */ + +#ifndef CPU_OPS_H +#define CPU_OPS_H + +#include + +#define CPU_IMPL_PN_MASK (MIDR_IMPL_MASK << MIDR_IMPL_SHIFT) | \ + (MIDR_PN_MASK << MIDR_PN_SHIFT) + +/* Hardcode to keep compatible with assembly. sizeof(uintptr_t) */ +#if __aarch64__ +#define CPU_WORD_SIZE 8 +#else +#define CPU_WORD_SIZE 4 +#endif /* __aarch64__ */ + +/* The number of CPU operations allowed */ +#define CPU_MAX_PWR_DWN_OPS 2 +/* Special constant to specify that CPU has no reset function */ +#define CPU_NO_RESET_FUNC 0 + +#if __aarch64__ +#define CPU_NO_EXTRA1_FUNC 0 +#define CPU_NO_EXTRA2_FUNC 0 +#define CPU_NO_EXTRA3_FUNC 0 +#endif /* __aarch64__ */ + + +/* + * Define the sizes of the fields in the cpu_ops structure. Word size is set per + * Aarch so keep these definitions the same and each can include whatever it + * needs. + */ +#define CPU_MIDR_SIZE CPU_WORD_SIZE +#ifdef IMAGE_AT_EL3 +#define CPU_RESET_FUNC_SIZE CPU_WORD_SIZE +#else +#define CPU_RESET_FUNC_SIZE 0 +#endif /* IMAGE_AT_EL3 */ +#define CPU_EXTRA1_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA2_FUNC_SIZE CPU_WORD_SIZE +#define CPU_EXTRA3_FUNC_SIZE CPU_WORD_SIZE +#define CPU_E_HANDLER_FUNC_SIZE CPU_WORD_SIZE +/* The power down core and cluster is needed only in BL31 and BL32 */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_PWR_DWN_OPS_SIZE CPU_WORD_SIZE * CPU_MAX_PWR_DWN_OPS +#else +#define CPU_PWR_DWN_OPS_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ + +/* Fields required to print errata status */ +#if REPORT_ERRATA +#define CPU_ERRATA_FUNC_SIZE CPU_WORD_SIZE +/* BL1 doesn't require mutual exclusion and printed flag. */ +#if defined(IMAGE_BL31) || defined(IMAGE_BL32) +#define CPU_ERRATA_LOCK_SIZE CPU_WORD_SIZE +#define CPU_ERRATA_PRINTED_SIZE CPU_WORD_SIZE +#else +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* defined(IMAGE_BL31) || defined(IMAGE_BL32) */ +#else +#define CPU_ERRATA_FUNC_SIZE 0 +#define CPU_ERRATA_LOCK_SIZE 0 +#define CPU_ERRATA_PRINTED_SIZE 0 +#endif /* REPORT_ERRATA */ + +#if defined(IMAGE_BL31) && CRASH_REPORTING +#define CPU_REG_DUMP_SIZE CPU_WORD_SIZE +#else +#define CPU_REG_DUMP_SIZE 0 +#endif /* defined(IMAGE_BL31) && CRASH_REPORTING */ + + +/* + * Define the offsets to the fields in cpu_ops structure. Every offset is + * defined based on the offset and size of the previous field. + */ +#define CPU_MIDR 0 +#define CPU_RESET_FUNC CPU_MIDR + CPU_MIDR_SIZE +#if __aarch64__ +#define CPU_EXTRA1_FUNC CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#define CPU_EXTRA2_FUNC CPU_EXTRA1_FUNC + CPU_EXTRA1_FUNC_SIZE +#define CPU_EXTRA3_FUNC CPU_EXTRA2_FUNC + CPU_EXTRA2_FUNC_SIZE +#define CPU_E_HANDLER_FUNC CPU_EXTRA3_FUNC + CPU_EXTRA3_FUNC_SIZE +#define CPU_PWR_DWN_OPS CPU_E_HANDLER_FUNC + CPU_E_HANDLER_FUNC_SIZE +#else +#define CPU_PWR_DWN_OPS CPU_RESET_FUNC + CPU_RESET_FUNC_SIZE +#endif /* __aarch64__ */ +#define CPU_ERRATA_FUNC CPU_PWR_DWN_OPS + CPU_PWR_DWN_OPS_SIZE +#define CPU_ERRATA_LOCK CPU_ERRATA_FUNC + CPU_ERRATA_FUNC_SIZE +#define CPU_ERRATA_PRINTED CPU_ERRATA_LOCK + CPU_ERRATA_LOCK_SIZE +#if __aarch64__ +#define CPU_REG_DUMP CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#define CPU_OPS_SIZE CPU_REG_DUMP + CPU_REG_DUMP_SIZE +#else +#define CPU_OPS_SIZE CPU_ERRATA_PRINTED + CPU_ERRATA_PRINTED_SIZE +#endif /* __aarch64__ */ + +#endif /* CPU_OPS_H */ diff --git a/lib/cpus/aarch32/cpu_helpers.S b/lib/cpus/aarch32/cpu_helpers.S index e25ce2a59..25b6308dd 100644 --- a/lib/cpus/aarch32/cpu_helpers.S +++ b/lib/cpus/aarch32/cpu_helpers.S @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include diff --git a/lib/cpus/aarch64/cpu_helpers.S b/lib/cpus/aarch64/cpu_helpers.S index 0a03e381f..6fe30d559 100644 --- a/lib/cpus/aarch64/cpu_helpers.S +++ b/lib/cpus/aarch64/cpu_helpers.S @@ -10,6 +10,7 @@ #include #include #include +#include #include #include