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https://github.com/ARM-software/arm-trusted-firmware.git
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fdts: n1sdp: DTS file for single-chip and multi-chip environment.
N1SDP supports both single-chip and multi-chip environment. Added DTS file for both type of environment. Enabled DTS files compilation for N1SDP platform. Change-Id: I66af88dcfb841893eb6ed2ca18d3025de81236a0 Co-authored-by: Robin Murphy <Robin.Murphy@arm.com> Co-authored-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com> Co-authored-by: Manoj Kumar <manoj.kumar3@arm.com> Co-authored-by: Anurag Koul <anurag.koul@arm.com> Signed-off-by: Sayanta Pattanayak <sayanta.pattanayak@arm.com>
This commit is contained in:
Andre Przywara
Sayanta Pattanayak
parent
4db3a8870a
commit
000653b467
4 changed files with 367 additions and 0 deletions
63
fdts/n1sdp-multi-chip.dts
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63
fdts/n1sdp-multi-chip.dts
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@ -0,0 +1,63 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2019-2020, Arm Limited.
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*/
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#include "n1sdp-single-chip.dts"
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/ {
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cpus {
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cpu4@100000000 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu5@100000100 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00000100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu6@100010000 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00010000>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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cpu7@100010100 {
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compatible = "arm,neoverse-n1";
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reg = <0x1 0x00010100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <1>;
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};
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};
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/* Remote N1SDP board address is mapped at offset 4TB.
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* First DRAM Bank of remote N1SDP board is mapped at 4TB + 2GB.
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*/
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memory@40080000000 {
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device_type = "memory";
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reg = <0x00000400 0x80000000 0x0 0x80000000>,
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<0x00000480 0x80000000 0x3 0x80000000>;
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numa-node-id = <1>;
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};
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distance-map {
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compatible = "numa-distance-map-v1";
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distance-matrix = <0 0 10>,
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<0 1 20>,
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<1 1 10>;
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};
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};
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&gic {
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#redistributor-regions = <2>;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>, /* GICR */
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<0x400 0x300c0000 0 0x80000>; /* GICR */
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};
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92
fdts/n1sdp-single-chip.dts
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92
fdts/n1sdp-single-chip.dts
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@ -0,0 +1,92 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2019-2020, Arm Limited.
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*/
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/dts-v1/;
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#include "n1sdp.dtsi"
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/ {
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model = "Arm Neoverse N1 System Development Platform";
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compatible = "arm,neoverse-n1-sdp", "arm,neoverse-n1-soc";
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aliases {
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serial0 = &soc_uart0;
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};
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chosen {
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stdout-path = "soc_uart0:115200n8";
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};
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/* This configuration assumes that standard setup with two DIMM modules.
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* In the first 2GB of DRAM bank the top 16MB are reserved by firmware as secure memory.
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* This configuration assumes 16GB of total DRAM being populated.
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*/
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memory@80000000 {
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device_type = "memory";
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reg = <0x00000000 0x80000000 0x0 0x7f000000>,
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<0x00000080 0x80000000 0x3 0x80000000>;
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numa-node-id = <0>;
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};
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soc_refclk60mhz: refclk60mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <60000000>;
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clock-output-names = "iofpga_clk";
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};
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soc_hdlcdclk: hdlcdclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <23750000>;
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clock-output-names = "hdlcdclk";
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};
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hdlcd: hdlcd@1c050000 {
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compatible = "arm,hdlcd";
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reg = <0 0x1c050000 0 0x1000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_hdlcdclk>;
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clock-names = "pxlclk";
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port {
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hdlcd0_output: endpoint {
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remote-endpoint = <&tda998x_0_input>;
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};
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};
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};
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i2c@1c0f0000 {
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compatible = "arm,versatile-i2c";
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reg = <0x0 0x1c0f0000 0x0 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <400000>;
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i2c-sda-hold-time-ns = <500>;
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clocks = <&soc_refclk60mhz>;
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hdmi-transmitter@70 {
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compatible = "nxp,tda998x";
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reg = <0x70>;
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port {
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tda998x_0_input: endpoint {
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remote-endpoint = <&hdlcd0_output>;
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};
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};
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};
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};
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};
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&pcie_ctlr {
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status = "okay";
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};
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&ccix_pcie_ctlr {
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status = "okay";
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};
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&soc_uart0 {
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status = "okay";
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};
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210
fdts/n1sdp.dtsi
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210
fdts/n1sdp.dtsi
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@ -0,0 +1,210 @@
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// SPDX-License-Identifier: (GPL-2.0 or BSD-3-Clause)
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/*
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* Copyright (c) 2019-2020, Arm Limited.
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*/
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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/ {
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu0@0 {
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compatible = "arm,neoverse-n1";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <0>;
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};
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cpu1@100 {
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compatible = "arm,neoverse-n1";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <0>;
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};
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cpu2@10000 {
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compatible = "arm,neoverse-n1";
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reg = <0x0 0x10000>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <0>;
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};
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cpu3@10100 {
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compatible = "arm,neoverse-n1";
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reg = <0x0 0x10100>;
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device_type = "cpu";
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enable-method = "psci";
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numa-node-id = <0>;
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};
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};
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pmu {
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compatible = "arm,armv8-pmuv3";
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interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
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};
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spe-pmu {
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compatible = "arm,statistical-profiling-extension-v1";
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interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
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};
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psci {
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compatible = "arm,psci-0.2";
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method = "smc";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>,
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<GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>;
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};
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soc_refclk100mhz: refclk100mhz {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <100000000>;
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clock-output-names = "apb_pclk";
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};
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soc_uartclk: uartclk {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <50000000>;
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clock-output-names = "uartclk";
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};
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soc {
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compatible = "arm,neoverse-n1-soc", "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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gic: interrupt-controller@30000000 {
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compatible = "arm,gic-v3";
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#address-cells = <2>;
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#interrupt-cells = <3>;
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#size-cells = <2>;
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ranges;
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interrupt-controller;
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reg = <0x0 0x30000000 0 0x10000>, /* GICD */
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<0x0 0x300c0000 0 0x80000>; /* GICR */
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interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
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its1: its@30040000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30040000 0x0 0x20000>;
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};
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its2: its@30060000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30060000 0x0 0x20000>;
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};
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its_ccix: its@30080000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x30080000 0x0 0x20000>;
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};
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its_pcie: its@300a0000 {
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compatible = "arm,gic-v3-its";
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msi-controller;
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#msi-cells = <1>;
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reg = <0x0 0x300a0000 0x0 0x20000>;
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};
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};
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smmu_ccix: iommu@4f000000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x4f000000 0 0x40000>;
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interrupts = <GIC_SPI 228 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 229 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 230 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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msi-parent = <&its1 0>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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smmu_pcie: iommu@4f400000 {
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compatible = "arm,smmu-v3";
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reg = <0 0x4f400000 0 0x40000>;
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interrupts = <GIC_SPI 235 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 236 IRQ_TYPE_EDGE_RISING>,
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<GIC_SPI 237 IRQ_TYPE_EDGE_RISING>;
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interrupt-names = "eventq", "cmdq-sync", "gerror";
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msi-parent = <&its2 0>;
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#iommu-cells = <1>;
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dma-coherent;
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};
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pcie_ctlr: pcie@70000000 {
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compatible = "arm,n1sdp-pcie";
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device_type = "pci";
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reg = <0 0x70000000 0 0x1200000>;
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bus-range = <0 17>;
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linux,pci-domain = <0>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x00 0x75200000 0x00 0x00010000>,
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<0x02000000 0x00 0x71200000 0x00 0x71200000 0x00 0x04000000>,
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<0x42000000 0x09 0x00000000 0x09 0x00000000 0x20 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 169 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 0 170 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 0 171 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 0 172 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0 &its_pcie 0 0x10000>;
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iommu-map = <0 &smmu_pcie 0 0x10000>;
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status = "disabled";
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};
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ccix_pcie_ctlr: pcie@68000000 {
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compatible = "arm,n1sdp-pcie";
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device_type = "pci";
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reg = <0 0x68000000 0 0x1200000>;
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bus-range = <0 17>;
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linux,pci-domain = <1>;
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#address-cells = <3>;
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#size-cells = <2>;
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dma-coherent;
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ranges = <0x01000000 0x00 0x00000000 0x00 0x6d200000 0x00 0x00010000>,
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<0x02000000 0x00 0x69200000 0x00 0x69200000 0x00 0x04000000>,
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<0x42000000 0x29 0x00000000 0x29 0x00000000 0x20 0x00000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 0 7>;
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interrupt-map = <0 0 0 1 &gic 0 0 0 201 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 2 &gic 0 0 0 202 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 3 &gic 0 0 0 203 IRQ_TYPE_LEVEL_HIGH>,
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<0 0 0 4 &gic 0 0 0 204 IRQ_TYPE_LEVEL_HIGH>;
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msi-map = <0 &its_ccix 0 0x10000>;
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iommu-map = <0 &smmu_ccix 0 0x10000>;
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status = "disabled";
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};
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soc_uart0: serial@2a400000 {
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compatible = "arm,pl011", "arm,primecell";
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reg = <0x0 0x2a400000 0x0 0x1000>;
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interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&soc_uartclk>, <&soc_refclk100mhz>;
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clock-names = "uartclk", "apb_pclk";
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status = "disabled";
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};
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};
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};
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@ -38,6 +38,8 @@ BL31_SOURCES := ${N1SDP_CPU_SOURCES} \
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${N1SDP_BASE}/n1sdp_security.c \
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drivers/arm/css/sds/sds.c
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FDT_SOURCES += fdts/${PLAT}-single-chip.dts \
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fdts/${PLAT}-multi-chip.dts
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# TF-A not required to load the SCP Images
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override CSS_LOAD_SCP_IMAGES := 0
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